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openwrtv4/target/linux/lantiq/patches/105-header_xway.patch

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adds new lantiq kernel. once the codebase is fully tested and know to be working on all the devices previously supported by ifxmips, we will drop ifxmips support. SVN-Revision: 24526
2010-12-12 22:57:16 +00:00
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -0,0 +1,18 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef __LANTIQ_IRQ_H
+#define __LANTIQ_IRQ_H
+
+#include <xway_irq.h>
+
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
@@ -0,0 +1,155 @@
+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
+
+
+/******************************************************************************
+ Copyright (c) 2002, Infineon Technologies. All rights reserved.
+
+ No Warranty
+ Because the program is licensed free of charge, there is no warranty for
+ the program, to the extent permitted by applicable law. Except when
+ otherwise stated in writing the copyright holders and/or other parties
+ provide the program "as is" without warranty of any kind, either
+ expressed or implied, including, but not limited to, the implied
+ warranties of merchantability and fitness for a particular purpose. The
+ entire risk as to the quality and performance of the program is with
+ you. should the program prove defective, you assume the cost of all
+ necessary servicing, repair or correction.
+
+ In no event unless required by applicable law or agreed to in writing
+ will any copyright holder, or any other party who may modify and/or
+ redistribute the program as permitted above, be liable to you for
+ damages, including any general, special, incidental or consequential
+ damages arising out of the use or inability to use the program
+ (including but not limited to loss of data or data being rendered
+ inaccurate or losses sustained by you or third parties or a failure of
+ the program to operate with any other programs), even if such holder or
+ other party has been advised of the possibility of such damages.
+******************************************************************************/
+
+
+/*
+ * ####################################
+ * Definition
+ * ####################################
+ */
+
+/*
+ * Available Timer/Counter Index
+ */
+#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
+#define TIMER_ANY 0x00
+#define TIMER1A TIMER(1, 0)
+#define TIMER1B TIMER(1, 1)
+#define TIMER2A TIMER(2, 0)
+#define TIMER2B TIMER(2, 1)
+#define TIMER3A TIMER(3, 0)
+#define TIMER3B TIMER(3, 1)
+
+/*
+ * Flag of Timer/Counter
+ * These flags specify the way in which timer is configured.
+ */
+/* Bit size of timer/counter. */
+#define TIMER_FLAG_16BIT 0x0000
+#define TIMER_FLAG_32BIT 0x0001
+/* Switch between timer and counter. */
+#define TIMER_FLAG_TIMER 0x0000
+#define TIMER_FLAG_COUNTER 0x0002
+/* Stop or continue when overflowing/underflowing. */
+#define TIMER_FLAG_ONCE 0x0000
+#define TIMER_FLAG_CYCLIC 0x0004
+/* Count up or counter down. */
+#define TIMER_FLAG_UP 0x0000
+#define TIMER_FLAG_DOWN 0x0008
+/* Count on specific level or edge. */
+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
+#define TIMER_FLAG_RISE_EDGE 0x0010
+#define TIMER_FLAG_FALL_EDGE 0x0020
+#define TIMER_FLAG_ANY_EDGE 0x0030
+/* Signal is syncronous to module clock or not. */
+#define TIMER_FLAG_UNSYNC 0x0000
+#define TIMER_FLAG_SYNC 0x0080
+/* Different interrupt handle type. */
+#define TIMER_FLAG_NO_HANDLE 0x0000
+#if defined(__KERNEL__)
+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
+#endif // defined(__KERNEL__)
+#define TIMER_FLAG_SIGNAL 0x0300
+/* Internal clock source or external clock source */
+#define TIMER_FLAG_INT_SRC 0x0000
+#define TIMER_FLAG_EXT_SRC 0x1000
+
+
+/*
+ * ioctl Command
+ */
+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
+
+/*
+ * Data Type Used to Call ioctl
+ */
+struct gptu_ioctl_param {
+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
+ * GPTU_SET_COUNTER, this field is ID of expected *
+ * timer/counter. If it's zero, a timer/counter would *
+ * be dynamically allocated and ID would be stored in *
+ * this field. *
+ * In command GPTU_GET_COUNT_VALUE, this field is *
+ * ignored. *
+ * In other command, this field is ID of timer/counter *
+ * allocated. */
+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
+ * GPTU_SET_COUNTER, this field contains flags to *
+ * specify how to configure timer/counter. *
+ * In command GPTU_START_TIMER, zero indicate start *
+ * and non-zero indicate resume timer/counter. *
+ * In other command, this field is ignored. */
+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
+ * init/reload value. *
+ * In command GPTU_SET_TIMER, this field contains *
+ * frequency (0.001Hz) of timer. *
+ * In command GPTU_GET_COUNT_VALUE, current count *
+ * value would be stored in this field. *
+ * In command GPTU_CALCULATE_DIVIDER, this field *
+ * contains frequency wanted, and after calculation, *
+ * divider would be stored in this field to overwrite *
+ * the frequency. *
+ * In other command, this field is ignored. */
+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
+ * if signal is required, this field contains process *
+ * ID to which signal would be sent. *
+ * In other command, this field is ignored. */
+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
+ * if signal is required, this field contains signal *
+ * number which would be sent. *
+ * In other command, this field is ignored. */
+};
+
+/*
+ * ####################################
+ * Data Type
+ * ####################################
+ */
+typedef void (*timer_callback)(unsigned long arg);
+
* fix usb compile warnings * fix timer header file which broke compile of external tapi driver * rebase patch SVN-Revision: 25344
2011-02-03 17:34:55 +00:00
+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
+extern int lq_free_timer(unsigned int);
+extern int lq_start_timer(unsigned int, int);
+extern int lq_stop_timer(unsigned int);
+extern int lq_reset_counter_flags(u32 timer, u32 flags);
+extern int lq_get_count_value(unsigned int, unsigned long *);
+extern u32 lq_cal_divider(unsigned long);
+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
+extern int lq_set_counter(unsigned int timer, unsigned int flag,
adds new lantiq kernel. once the codebase is fully tested and know to be working on all the devices previously supported by ifxmips, we will drop ifxmips support. SVN-Revision: 24526
2010-12-12 22:57:16 +00:00
+ u32 reload, unsigned long arg1, unsigned long arg2);
+
+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway.h
@@ -0,0 +1,121 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2005 infineon
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+
+#ifndef _LQ_XWAY_H__
+#define _LQ_XWAY_H__
+
+#include <lantiq.h>
+
+/* request a non-gpio and set the PIO config */
+extern int lq_gpio_request(unsigned int pin, unsigned int alt0,
+ unsigned int alt1, unsigned int dir, const char *name);
+extern int lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val);
+
+extern void lq_pmu_enable(unsigned int module);
+extern void lq_pmu_disable(unsigned int module);
+
+extern unsigned int lq_get_fpi_bus_clock(int bus);
+
+#define BOARD_SYSTEM_TYPE "LANTIQ"
+
+/*------------ Chip IDs */
+#define SOC_ID_DANUBE1 0x129
+#define SOC_ID_DANUBE2 0x12B
+#define SOC_ID_TWINPASS 0x12D
+#define SOC_ID_ARX188 0x16C
+#define SOC_ID_ARX168 0x16D
+#define SOC_ID_ARX182 0x16F
+
+/*------------ SoC Types */
+#define SOC_TYPE_DANUBE 0x01
+#define SOC_TYPE_TWINPASS 0x02
+#define SOC_TYPE_AR9 0x03
+
+/*------------ ASC0/1 */
+#define LQ_ASC0_BASE 0x1E100400
+#define LQ_ASC1_BASE 0x1E100C00
+#define LQ_ASC_SIZE 0x400
+
+/*------------ RCU */
+#define LQ_RCU_BASE_ADDR 0xBF203000
+
+/*------------ GPTU */
+#define LQ_GPTU_BASE_ADDR 0xB8000300
+
+/*------------ EBU */
+#define LQ_EBU_GPIO_START 0x14000000
+#define LQ_EBU_GPIO_SIZE 0x1000
+
+#define LQ_EBU_BASE_ADDR 0xBE105300
+
+#define LQ_EBU_BUSCON0 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0060))
+#define LQ_EBU_PCC_CON ((u32 *)(LQ_EBU_BASE_ADDR + 0x0090))
+#define LQ_EBU_PCC_IEN ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A4))
+#define LQ_EBU_PCC_ISTAT ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A0))
+#define LQ_EBU_BUSCON1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0064))
+#define LQ_EBU_ADDRSEL1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0024))
+
+#define EBU_WRDIS 0x80000000
+
+/*------------ CGU */
+#define LQ_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
+
+/*------------ PMU */
+#define LQ_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
+
+#define PMU_DMA 0x0020
+#define PMU_USB 0x8041
+#define PMU_LED 0x0800
+#define PMU_GPT 0x1000
+#define PMU_PPE 0x2000
+#define PMU_FPI 0x4000
+#define PMU_SWITCH 0x10000000
+
+/*------------ ETOP */
+#define LQ_PPE32_BASE_ADDR 0xBE180000
+#define LQ_PPE32_SIZE 0x40000
+
+/*------------ DMA */
+#define LQ_DMA_BASE_ADDR 0xBE104100
+
+/*------------ PCI */
+#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
+#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
+
+/*------------ WDT */
+#define LQ_WDT_BASE 0x1F880000
+#define LQ_WDT_SIZE 0x400
+
+/*------------ Serial To Parallel conversion */
+#define LQ_STP_BASE 0x1E100BB0
+#define LQ_STP_SIZE 0x40
+
+/*------------ GPIO */
+#define LQ_GPIO0_BASE_ADDR 0x1E100B10
+#define LQ_GPIO1_BASE_ADDR 0x1E100B40
+#define LQ_GPIO_SIZE 0x30
+
+/*------------ SSC */
+#define LQ_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
+
+/*------------ MEI */
+#define LQ_MEI_BASE_ADDR (KSEG1 + 0x1E116000)
+
+/*------------ DEU */
+#define LQ_DEU_BASE (KSEG1 + 0x1E103100)
+
+/*------------ MPS */
+#define LQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
+#define LQ_MPS_CHIPID ((u32 *)(LQ_MPS_BASE_ADDR + 0x0344))
+
+#endif
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
* make the usb gpio configurable * 105-header_xway.patch has a corrupt line count in it SVN-Revision: 24564
2010-12-14 13:02:49 +00:00
@@ -0,0 +1,194 @@
adds new lantiq kernel. once the codebase is fully tested and know to be working on all the devices previously supported by ifxmips, we will drop ifxmips support. SVN-Revision: 24526
2010-12-12 22:57:16 +00:00
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2005 infineon
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ *
+ */
+#ifndef _LQ_DMA_H__
+#define _LQ_DMA_H__
+
+#define RCV_INT 1
+#define TX_BUF_FULL_INT 2
+#define TRANSMIT_CPT_INT 4
+#define LQ_DMA_CH_ON 1
+#define LQ_DMA_CH_OFF 0
+#define LQ_DMA_CH_DEFAULT_WEIGHT 100
+
+enum attr_t{
+ TX = 0,
+ RX = 1,
+ RESERVED = 2,
+ DEFAULT = 3,
+};
+
+#define DMA_OWN 1
+#define CPU_OWN 0
+#define DMA_MAJOR 250
+
+#define DMA_DESC_OWN_CPU 0x0
+#define DMA_DESC_OWN_DMA 0x80000000
+#define DMA_DESC_CPT_SET 0x40000000
+#define DMA_DESC_SOP_SET 0x20000000
+#define DMA_DESC_EOP_SET 0x10000000
+
+#define MISCFG_MASK 0x40
+#define RDERR_MASK 0x20
+#define CHOFF_MASK 0x10
+#define DESCPT_MASK 0x8
+#define DUR_MASK 0x4
+#define EOP_MASK 0x2
+
+#define DMA_DROP_MASK (1<<31)
+
+#define LQ_DMA_RX -1
+#define LQ_DMA_TX 1
+
+struct dma_chan_map {
+ const char *dev_name;
+ enum attr_t dir;
+ int pri;
+ int irq;
+ int rel_chan_no;
+};
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+struct rx_desc {
+ u32 data_length:16;
+ volatile u32 reserved:7;
+ volatile u32 byte_offset:2;
+ volatile u32 Burst_length_offset:3;
+ volatile u32 EoP:1;
+ volatile u32 Res:1;
+ volatile u32 C:1;
+ volatile u32 OWN:1;
+ volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
+};
+
+struct tx_desc {
+ volatile u32 data_length:16;
+ volatile u32 reserved1:7;
+ volatile u32 byte_offset:5;
+ volatile u32 EoP:1;
+ volatile u32 SoP:1;
+ volatile u32 C:1;
+ volatile u32 OWN:1;
+ volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
+};
+#else /* BIG */
+struct rx_desc {
+ union {
+ struct {
+ volatile u32 OWN:1;
+ volatile u32 C:1;
+ volatile u32 SoP:1;
+ volatile u32 EoP:1;
+ volatile u32 Burst_length_offset:3;
+ volatile u32 byte_offset:2;
+ volatile u32 reserve:7;
+ volatile u32 data_length:16;
+ } field;
+ volatile u32 word;
+ } status;
+ volatile u32 Data_Pointer;
+};
+
+struct tx_desc {
+ union {
+ struct {
+ volatile u32 OWN:1;
+ volatile u32 C:1;
+ volatile u32 SoP:1;
+ volatile u32 EoP:1;
+ volatile u32 byte_offset:5;
+ volatile u32 reserved:7;
+ volatile u32 data_length:16;
+ } field;
+ volatile u32 word;
+ } status;
+ volatile u32 Data_Pointer;
+};
+#endif /* ENDIAN */
+
+struct dma_channel_info {
+ /* relative channel number */
+ int rel_chan_no;
+ /* class for this channel for QoS */
+ int pri;
+ /* specify byte_offset */
+ int byte_offset;
+ /* direction */
+ int dir;
+ /* irq number */
+ int irq;
+ /* descriptor parameter */
+ int desc_base;
+ int desc_len;
+ int curr_desc;
+ int prev_desc; /* only used if it is a tx channel*/
+ /* weight setting for WFQ algorithm*/
+ int weight;
+ int default_weight;
+ int packet_size;
+ int burst_len;
+ /* on or off of this channel */
+ int control;
+ /* optional information for the upper layer devices */
+#if defined(CONFIG_LQ_ETHERNET_D2) || defined(CONFIG_LQ_PPA)
+ void *opt[64];
+#else
+ void *opt[25];
+#endif
+ /* Pointer to the peripheral device who is using this channel */
+ void *dma_dev;
+ /* channel operations */
+ void (*open)(struct dma_channel_info *pCh);
+ void (*close)(struct dma_channel_info *pCh);
+ void (*reset)(struct dma_channel_info *pCh);
+ void (*enable_irq)(struct dma_channel_info *pCh);
+ void (*disable_irq)(struct dma_channel_info *pCh);
+};
+
+struct dma_device_info {
+ /* device name of this peripheral */
+ char device_name[15];
+ int reserved;
+ int tx_burst_len;
+ int rx_burst_len;
+ int default_weight;
+ int current_tx_chan;
+ int current_rx_chan;
+ int num_tx_chan;
+ int num_rx_chan;
+ int max_rx_chan_num;
+ int max_tx_chan_num;
+ struct dma_channel_info *tx_chan[20];
+ struct dma_channel_info *rx_chan[20];
+ /*functions, optional*/
+ u8 *(*buffer_alloc)(int len, int *offset, void **opt);
+ void (*buffer_free)(u8 *dataptr, void *opt);
+ int (*intr_handler)(struct dma_device_info *info, int status);
+ void *priv; /* used by peripheral driver only */
+};
+
+struct dma_device_info *dma_device_reserve(char *dev_name);
+void dma_device_release(struct dma_device_info *dev);
+void dma_device_register(struct dma_device_info *info);
+void dma_device_unregister(struct dma_device_info *info);
+int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
+int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
+ void *opt);
+
+#endif
+
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_irq.h
@@ -0,0 +1,62 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_XWAY_IRQ_H__
+#define _LANTIQ_XWAY_IRQ_H__
+
+#define INT_NUM_IRQ0 8
+#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
+#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
+#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
+#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
+#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define LQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7))
+#define LQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2)
+#define LQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3)
+
+#define LQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
+#define LQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
+#define LQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
+
+#define LQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
+#define LQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
+
+#define LQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
+#define LQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
+#define LQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
+
+#define MIPS_CPU_TIMER_IRQ 7
+
+#define LQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
+#define LQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
+#define LQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
+#define LQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
+#define LQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
+#define LQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
+#define LQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
+#define LQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
+#define LQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
+#define LQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
+#define LQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
+#define LQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
+#define LQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
+#define LQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
+#define LQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
+#define LQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
+#define LQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
+#define LQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
+#define LQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
+#define LQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
+
+#define LQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
+
+#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
+
+#endif
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