125 lines
3 KiB
Diff
125 lines
3 KiB
Diff
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--- a/cpu/mips/start.S
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+++ b/cpu/mips/start.S
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@@ -69,6 +69,9 @@ _start:
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#elif defined(CONFIG_PURPLE)
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.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
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.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
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+#elif defined(CONFIG_SYS_EBU_BOOT)
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+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
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+ .word 0x00000000 /* phase of the flash */
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#else
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RVECENT(romReserved,2)
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#endif
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@@ -202,7 +205,25 @@ _start:
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* 128 * 8 == 1024 == 0x400
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* so this is address R_VEC+0x400 == 0xbfc00400
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*/
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-#ifdef CONFIG_PURPLE
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+#ifndef CONFIG_PURPLE
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+ XVECENT(romExcHandle,0x400); /* bfc00400: Int, CauseIV=1 */
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+ RVECENT(romReserved,129);
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+ RVECENT(romReserved,130);
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+ RVECENT(romReserved,131);
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+ RVECENT(romReserved,132);
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+ RVECENT(romReserved,133);
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+ RVECENT(romReserved,134);
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+ RVECENT(romReserved,135);
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+ RVECENT(romReserved,136);
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+ RVECENT(romReserved,137);
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+ RVECENT(romReserved,138);
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+ RVECENT(romReserved,139);
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+ RVECENT(romReserved,140);
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+ RVECENT(romReserved,141);
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+ RVECENT(romReserved,142);
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+ RVECENT(romReserved,143);
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+ XVECENT(romExcHandle,0x480); /* bfc00480: EJTAG debug exception */
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+#else /* CONFIG_PURPLE */
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/* 0xbfc00400 */
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.word 0xdc870000
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.word 0xfca70000
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@@ -228,6 +249,12 @@ _start:
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#endif /* CONFIG_PURPLE */
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.align 4
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reset:
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+#ifdef CONFIG_SYS_MIPS_MULTI_CPU
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+ mfc0 k0, CP0_EBASE
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+ and k0, EBASEF_CPUNUM
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+ bne k0, zero, ifx_mips_handler_cpux
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+ nop
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+#endif
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/* Clear watch registers.
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*/
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@@ -239,6 +266,16 @@ reset:
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setup_c0_status_reset
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+#if defined(CONFIG_MIPS24KEC) || defined(CONFIG_MIPS34KC)
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+ /* CONFIG7 register */
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+ /* Erratum "RPS May Cause Incorrect Instruction Execution"
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+ * for 24KEC and 34KC */
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+ mfc0 k0, CP0_CONFIG, 7
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+ li k1, MIPS_CONF7_RPS
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+ or k0, k1
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+ mtc0 k0, CP0_CONFIG, 7
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+#endif
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+
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/* Init Timer */
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mtc0 zero, CP0_COUNT
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mtc0 zero, CP0_COMPARE
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@@ -270,9 +307,12 @@ reset:
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jalr t9
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nop
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+#ifndef CONFIG_SYS_MIPS_CACHE_OPER_MODE
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+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NONCOHERENT
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+#endif
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/* ... and enable them.
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*/
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- li t0, CONF_CM_CACHABLE_NONCOHERENT
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+ li t0, CONFIG_SYS_MIPS_CACHE_OPER_MODE
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mtc0 t0, CP0_CONFIG
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
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@@ -419,3 +459,15 @@ romReserved:
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romExcHandle:
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b romExcHandle
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+
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+ /* Additional handlers.
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+ */
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+#ifdef CONFIG_SYS_MIPS_MULTI_CPU
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+/*
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+ * Stop Slave CPUs
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+ */
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+ifx_mips_handler_cpux:
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+ wait;
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+ b ifx_mips_handler_cpux;
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+ nop;
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+#endif
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--- a/include/asm-mips/mipsregs.h
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+++ b/include/asm-mips/mipsregs.h
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@@ -57,6 +57,7 @@
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#define CP0_CAUSE $13
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#define CP0_EPC $14
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#define CP0_PRID $15
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+#define CP0_EBASE $15,1
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#define CP0_CONFIG $16
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#define CP0_LLADDR $17
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#define CP0_WATCHLO $18
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@@ -395,6 +396,14 @@
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#define CAUSEF_BD (_ULCAST_(1) << 31)
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/*
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+ * Bits in the coprocessor 0 EBase register
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+ */
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+#define EBASEB_CPUNUM 0
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+#define EBASEF_CPUNUM (0x3ff << EBASEB_CPUNUM)
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+#define EBASEB_EXPBASE 12
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+#define EBASEF_EXPBASE (0x3ffff << EBASEB_EXPBASE)
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+
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+/*
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* Bits in the coprocessor 0 config register.
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*/
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/* Generic bits. */
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