74 lines
2 KiB
Diff
74 lines
2 KiB
Diff
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From 220d6c860e0c7853aea6509ea2b5a44463c9af8b Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Sat, 31 Aug 2013 23:07:24 +0200
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Subject: [PATCH] ARM: sun7i: Enable the I2C controllers
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The Allwinner A20 shares the same I2C controller than the one that could
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be found on earlier SoCs from Allwinner. There is only a few more of
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these controllers. Add all of them in the DTSI.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun7i-a20.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 45 insertions(+)
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diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
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index 2e39ed9..0d0ee15 100644
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -340,6 +340,51 @@
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status = "disabled";
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};
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+ i2c0: i2c@01c2ac00 {
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+ compatible = "allwinner,sun4i-i2c";
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+ reg = <0x01c2ac00 0x400>;
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+ interrupts = <0 7 1>;
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+ clocks = <&apb1_gates 0>;
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+ clock-frequency = <100000>;
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+ status = "disabled";
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+ };
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+
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+ i2c1: i2c@01c2b000 {
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+ compatible = "allwinner,sun4i-i2c";
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+ reg = <0x01c2b000 0x400>;
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+ interrupts = <0 8 1>;
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+ clocks = <&apb1_gates 1>;
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+ clock-frequency = <100000>;
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+ status = "disabled";
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+ };
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+
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+ i2c2: i2c@01c2b400 {
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+ compatible = "allwinner,sun4i-i2c";
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+ reg = <0x01c2b400 0x400>;
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+ interrupts = <0 9 1>;
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+ clocks = <&apb1_gates 2>;
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+ clock-frequency = <100000>;
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+ status = "disabled";
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+ };
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+
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+ i2c3: i2c@01c2b800 {
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+ compatible = "allwinner,sun4i-i2c";
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+ reg = <0x01c2b800 0x400>;
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+ interrupts = <0 88 1>;
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+ clocks = <&apb1_gates 3>;
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+ clock-frequency = <100000>;
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+ status = "disabled";
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+ };
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+
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+ i2c4: i2c@01c2bc00 {
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+ compatible = "allwinner,sun4i-i2c";
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+ reg = <0x01c2bc00 0x400>;
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+ interrupts = <0 89 1>;
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+ clocks = <&apb1_gates 15>;
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+ clock-frequency = <100000>;
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+ status = "disabled";
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+ };
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+
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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--
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1.8.4
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