59 lines
2.5 KiB
Diff
59 lines
2.5 KiB
Diff
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From edc5b23b8dd04980e0fa48fe79ba811b775cd2c2 Mon Sep 17 00:00:00 2001
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From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Date: Sat, 23 Apr 2016 12:34:59 +0530
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Subject: [PATCH 12/93] armv8: LSCH2 early and final mmu needs matching NS
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attribute
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When switching between the early and final mmu tables, the stack will
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get corrupted if the Non-Secure attribute is different. For ls1043a,
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this issue is currently masked because flush_dcache_all is called
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before the switch when CONFIG_SYS_DPAA_FMAN is defined.
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Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
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Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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---
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arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++++++++----
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1 file changed, 8 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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index a9dadfa..a7522da 100644
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--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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@@ -159,9 +159,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
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{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
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CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
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+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
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+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
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#endif
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};
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@@ -249,7 +251,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
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CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
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PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
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+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
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{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
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CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
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PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
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@@ -260,7 +263,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
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CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
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PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
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{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
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- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
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+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
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#endif
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};
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#endif
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--
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1.7.9.5
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