2017-02-07 11:32:35 +00:00
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From 807c16253319ee6ccf8873ae64f070f7eb532cd5 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jo=C3=ABl=20Esponde?= <joel.esponde@honeywell.com>
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Date: Wed, 23 Nov 2016 12:47:40 +0100
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Subject: [PATCH] mtd: spi-nor: fix spansion quad enable
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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With the S25FL127S nor flash part, each writing to the configuration
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register takes hundreds of ms. During that time, no more accesses to
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the flash should be done (even reads).
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This commit adds a wait loop after the register writing until the flash
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finishes its work.
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This issue could make rootfs mounting fail when the latter was done too
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much closely to this quad enable bit setting step. And in this case, a
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driver as UBIFS may try to recover the filesystem and may broke it
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completely.
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Signed-off-by: Joël Esponde <joel.esponde@honeywell.com>
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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2018-11-14 12:53:03 +00:00
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@@ -1269,6 +1269,13 @@ static int spansion_quad_enable(struct s
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2017-08-17 08:51:05 +00:00
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return ret;
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2017-02-07 11:32:35 +00:00
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}
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+ ret = spi_nor_wait_till_ready(nor);
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+ if (ret) {
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+ dev_err(nor->dev,
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+ "timeout while writing configuration register\n");
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+ return ret;
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+ }
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+
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/* read back and check it */
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ret = read_cr(nor);
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if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
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