127 lines
4.6 KiB
Diff
127 lines
4.6 KiB
Diff
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--- a/drivers/net/wireless/b43/phy_n.c
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+++ b/drivers/net/wireless/b43/phy_n.c
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@@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru
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#endif
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#ifdef CONFIG_B43_SSB
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case B43_BUS_SSB:
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- /* FIXME */
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+ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
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+ avoid);
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break;
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#endif
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}
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -675,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
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return 0;
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}
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}
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+
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+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
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+{
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+ u32 pmu_ctl = 0;
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+
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+ switch (cc->dev->bus->chip_id) {
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+ case 0x4322:
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
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+ if (spuravoid == 1)
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
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+ else
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
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+ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
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+ break;
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+ case 43222:
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+ /* TODO: BCM43222 requires updating PLLs too */
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+ return;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
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+ cc->dev->bus->chip_id);
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+ return;
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+ }
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+
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+ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
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+}
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+EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
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return (s8)gain;
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}
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+static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
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+{
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+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
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+ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
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+ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
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+ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
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+ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
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+ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
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+ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
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+ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
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+ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
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+ SSB_SPROM2_MAXP_A_LO_SHIFT);
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+}
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+
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static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
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SSB_SPROM1_ITSSI_A_SHIFT);
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SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
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SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
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- if (out->revision >= 2)
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- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+
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SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
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SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
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@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
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out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
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SSB_SPROM1_AGAIN_A,
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SSB_SPROM1_AGAIN_A_SHIFT);
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+ if (out->revision >= 2)
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+ sprom_extract_r23(out, in);
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}
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/* Revs 4 5 and 8 have partially shared layout */
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
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@@ -219,6 +219,7 @@
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#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
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#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
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#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
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+#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
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#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
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#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
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#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
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@@ -667,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
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void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
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enum ssb_pmu_ldo_volt_id id, u32 voltage);
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void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
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+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
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#endif /* LINUX_SSB_CHIPCO_H_ */
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -289,11 +289,11 @@
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#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
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#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
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#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
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-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
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-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
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-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
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+#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
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+#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
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+#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
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#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
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#define SSB_SPROM4_AGAIN0_SHIFT 0
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