2018-08-22 09:22:30 +00:00
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--- a/arch/mips/ath79/pci.c
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+++ b/arch/mips/ath79/pci.c
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2018-08-09 13:59:41 +00:00
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@@ -53,6 +53,15 @@ static const struct ath79_pci_irq ar724x
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}
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};
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+static const struct ath79_pci_irq qca953x_pci_irq_map[] __initconst = {
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+ {
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+ .bus = 0,
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+ .slot = 0,
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+ .pin = 1,
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+ .irq = ATH79_PCI_IRQ(0),
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+ },
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+};
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+
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static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
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{
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.bus = 0,
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@@ -98,6 +107,9 @@ int pcibios_map_irq(const struct pci_dev
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soc_is_ar9344()) {
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ath79_pci_irq_map = ar724x_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
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+ } else if (soc_is_qca953x()) {
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+ ath79_pci_irq_map = qca953x_pci_irq_map;
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+ ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map);
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} else if (soc_is_qca955x()) {
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ath79_pci_irq_map = qca955x_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
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@@ -303,6 +315,15 @@ int __init ath79_register_pci(void)
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AR724X_PCI_MEM_SIZE,
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0,
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ATH79_IP2_IRQ(0));
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+ } else if (soc_is_qca9533()) {
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+ pdev = ath79_register_pci_ar724x(0,
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+ QCA953X_PCI_CFG_BASE0,
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+ QCA953X_PCI_CTRL_BASE0,
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+ QCA953X_PCI_CRP_BASE0,
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+ QCA953X_PCI_MEM_BASE0,
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+ QCA953X_PCI_MEM_SIZE,
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+ 0,
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+ ATH79_IP2_IRQ(0));
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} else if (soc_is_qca9558()) {
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pdev = ath79_register_pci_ar724x(0,
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QCA955X_PCI_CFG_BASE0,
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