openwrtv4/package/devel/valgrind/patches/120-mips_fix_soft_float.patch

--- a/VEX/priv/guest_mips_helpers.c
+++ b/VEX/priv/guest_mips_helpers.c
@@ -1201,6 +1201,7 @@ extern UInt mips_dirtyhelper_calculate_F
                                                    flt_op inst )
 {
    UInt ret = 0;
+#ifndef __mips_soft_float
 #if defined(__mips__)
    VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
    UInt loFsVal, hiFsVal, loFtVal, hiFtVal;
@@ -1320,6 +1321,7 @@ extern UInt mips_dirtyhelper_calculate_F
          break;
    }
 #endif
+#endif
    return ret;
 }
 
@@ -1329,6 +1331,7 @@ extern UInt mips_dirtyhelper_calculate_F
                                                    flt_op inst )
 {
    UInt ret = 0;
+#ifndef __mips_soft_float
 #if defined(__mips__)
 #if defined(VGA_mips32)
    VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
@@ -1439,6 +1442,7 @@ extern UInt mips_dirtyhelper_calculate_F
          break;
    }
 #endif
+#endif
    return ret;
 }
 
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -1652,6 +1652,7 @@ Bool VG_(machine_get_hwcaps)( void )
         }
      }
 
+#ifndef __mips_soft_float
      /* Check if CPU has FPU and 32 dbl. prec. FP registers */
      int FIR = 0;
      __asm__ __volatile__(
@@ -1661,6 +1662,7 @@ Bool VG_(machine_get_hwcaps)( void )
      if (FIR & (1 << FP64)) {
         vai.hwcaps |= VEX_PRID_CPU_32FPR;
      }
+#endif
 
      VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act);
      VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);