77 lines
2.4 KiB
Diff
77 lines
2.4 KiB
Diff
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From 32bb743195e1e48c48fc5cefd7c6ecdce56046a3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Fri, 18 Jul 2014 15:58:44 -0300
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Subject: [PATCH] ARM: sunxi: Add PLL2 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit adds the PLL2 definition to the sun4i, sun5i and sun7i
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device trees. PLL2 is used to clock audio devices.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
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arch/arm/boot/dts/sun5i.dtsi | 8 ++++++++
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arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
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3 files changed, 24 insertions(+)
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diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
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index 30f663a..fab13af 100644
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--- a/arch/arm/boot/dts/sun4i-a10.dtsi
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+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
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@@ -195,6 +195,14 @@
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clock-output-names = "pll1";
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};
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+ pll2: clk@01c20008 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-a10-b-pll2-clk";
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+ reg = <0x01c20008 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
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+ };
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+
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
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index 53d3ead..a4b6a66 100644
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--- a/arch/arm/boot/dts/sun5i-a13.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
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@@ -102,6 +102,14 @@
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clock-output-names = "pll1";
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};
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+ pll2: clk@01c20008 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-a10-b-pll2-clk";
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+ reg = <0x01c20008 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
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+ };
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+
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
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index 7549f1b..12d9ffd 100644
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -199,6 +199,14 @@
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clock-output-names = "pll1";
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};
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+ pll2: clk@01c20008 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-a10-b-pll2-clk";
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+ reg = <0x01c20008 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
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+ };
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+
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-pll4-clk";
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