2012-02-13 15:17:59 +00:00
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/*
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* Ralink RT3662/RT3883 SoC specific setup
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/ramips_gpio.h>
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#include <asm/mach-ralink/rt3883.h>
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#include <asm/mach-ralink/rt3883_regs.h>
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void __iomem * rt3883_sysc_base;
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void __iomem * rt3883_memc_base;
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2012-03-11 19:05:53 +00:00
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void __init ramips_soc_prom_init(void)
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2012-02-13 15:17:59 +00:00
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{
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2012-03-11 19:05:53 +00:00
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
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2012-02-13 15:17:59 +00:00
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u32 n0;
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u32 n1;
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u32 id;
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2012-03-11 19:05:53 +00:00
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n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
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n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
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id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
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2012-02-13 15:17:59 +00:00
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snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %c%c%c%c%c%c%c%c ver:%u eco:%u",
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(char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
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(char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
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(char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
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(char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
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(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
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(id & RT3883_REVID_ECO_ID_MASK));
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2012-03-11 19:05:56 +00:00
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ramips_mem_base = RT3883_SDRAM_BASE;
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ramips_mem_size_min = RT3883_MEM_SIZE_MIN;
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ramips_mem_size_max = RT3883_MEM_SIZE_MAX;
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2012-02-13 15:17:59 +00:00
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}
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static struct ramips_gpio_chip rt3883_gpio_chips[] = {
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{
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.chip = {
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.label = "RT3883-GPIO0",
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.base = 0,
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.ngpio = 24,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x00,
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[RAMIPS_GPIO_REG_EDGE] = 0x04,
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[RAMIPS_GPIO_REG_RENA] = 0x08,
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[RAMIPS_GPIO_REG_FENA] = 0x0c,
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[RAMIPS_GPIO_REG_DATA] = 0x20,
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[RAMIPS_GPIO_REG_DIR] = 0x24,
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[RAMIPS_GPIO_REG_POL] = 0x28,
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[RAMIPS_GPIO_REG_SET] = 0x2c,
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[RAMIPS_GPIO_REG_RESET] = 0x30,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x34,
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},
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.map_base = RT3883_PIO_BASE,
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.map_size = RT3883_PIO_SIZE,
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},
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{
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.chip = {
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.label = "RT3883-GPIO1",
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.base = 24,
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.ngpio = 16,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x38,
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[RAMIPS_GPIO_REG_EDGE] = 0x3c,
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[RAMIPS_GPIO_REG_RENA] = 0x40,
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[RAMIPS_GPIO_REG_FENA] = 0x44,
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[RAMIPS_GPIO_REG_DATA] = 0x48,
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[RAMIPS_GPIO_REG_DIR] = 0x4c,
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[RAMIPS_GPIO_REG_POL] = 0x50,
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[RAMIPS_GPIO_REG_SET] = 0x54,
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[RAMIPS_GPIO_REG_RESET] = 0x58,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
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},
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.map_base = RT3883_PIO_BASE,
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.map_size = RT3883_PIO_SIZE,
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},
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{
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.chip = {
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.label = "RT3883-GPIO2",
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.base = 40,
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.ngpio = 32,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x60,
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[RAMIPS_GPIO_REG_EDGE] = 0x64,
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[RAMIPS_GPIO_REG_RENA] = 0x68,
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[RAMIPS_GPIO_REG_FENA] = 0x6c,
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[RAMIPS_GPIO_REG_DATA] = 0x70,
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[RAMIPS_GPIO_REG_DIR] = 0x74,
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[RAMIPS_GPIO_REG_POL] = 0x78,
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[RAMIPS_GPIO_REG_SET] = 0x7c,
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[RAMIPS_GPIO_REG_RESET] = 0x80,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x84,
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},
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.map_base = RT3883_PIO_BASE,
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.map_size = RT3883_PIO_SIZE,
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},
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{
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.chip = {
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.label = "RT3883-GPIO3",
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.base = 72,
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.ngpio = 24,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x88,
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[RAMIPS_GPIO_REG_EDGE] = 0x8c,
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[RAMIPS_GPIO_REG_RENA] = 0x90,
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[RAMIPS_GPIO_REG_FENA] = 0x94,
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[RAMIPS_GPIO_REG_DATA] = 0x98,
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[RAMIPS_GPIO_REG_DIR] = 0x9c,
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[RAMIPS_GPIO_REG_POL] = 0xa0,
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[RAMIPS_GPIO_REG_SET] = 0xa4,
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[RAMIPS_GPIO_REG_RESET] = 0xa8,
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[RAMIPS_GPIO_REG_TOGGLE] = 0xac,
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},
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.map_base = RT3883_PIO_BASE,
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.map_size = RT3883_PIO_SIZE,
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},
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};
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static struct ramips_gpio_data rt3883_gpio_data = {
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.chips = rt3883_gpio_chips,
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.num_chips = ARRAY_SIZE(rt3883_gpio_chips),
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};
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static void rt3883_gpio_reserve(int first, int last)
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{
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for (; first <= last; first++)
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gpio_request(first, "reserved");
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}
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void __init rt3883_gpio_init(u32 mode)
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{
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u32 t;
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rt3883_sysc_wr(mode, RT3883_SYSC_REG_GPIO_MODE);
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ramips_gpio_init(&rt3883_gpio_data);
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if ((mode & RT3883_GPIO_MODE_I2C) == 0)
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rt3883_gpio_reserve(RT3883_GPIO_I2C_SD, RT3883_GPIO_I2C_SCLK);
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if ((mode & RT3883_GPIO_MODE_SPI) == 0)
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rt3883_gpio_reserve(RT3883_GPIO_SPI_CS0, RT3883_GPIO_SPI_CLK);
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t = mode >> RT3883_GPIO_MODE_UART0_SHIFT;
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t &= RT3883_GPIO_MODE_UART0_MASK;
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switch (t) {
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case RT3883_GPIO_MODE_UARTF:
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case RT3883_GPIO_MODE_PCM_UARTF:
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case RT3883_GPIO_MODE_PCM_I2S:
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case RT3883_GPIO_MODE_I2S_UARTF:
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rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_14);
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break;
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case RT3883_GPIO_MODE_PCM_GPIO:
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rt3883_gpio_reserve(RT3883_GPIO_11, RT3883_GPIO_14);
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break;
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case RT3883_GPIO_MODE_GPIO_UARTF:
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case RT3883_GPIO_MODE_GPIO_I2S:
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rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_10);
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break;
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}
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if ((mode & RT3883_GPIO_MODE_UART1) == 0)
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rt3883_gpio_reserve(RT3883_GPIO_UART1_TXD,
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RT3883_GPIO_UART1_RXD);
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if ((mode & RT3883_GPIO_MODE_JTAG) == 0)
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rt3883_gpio_reserve(RT3883_GPIO_JTAG_TDO,
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RT3883_GPIO_JTAG_TCLK);
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if ((mode & RT3883_GPIO_MODE_MDIO) == 0)
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rt3883_gpio_reserve(RT3883_GPIO_MDIO_MDC,
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RT3883_GPIO_MDIO_MDIO);
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if ((mode & RT3883_GPIO_MODE_GE1) == 0)
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rt3883_gpio_reserve(RT3883_GPIO_GE1_TXD0,
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RT3883_GPIO_GE1_RXCLK);
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if ((mode & RT3883_GPIO_MODE_GE2) == 0)
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rt3883_gpio_reserve(RT3883_GPIO_GE2_TXD0,
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RT3883_GPIO_GE2_RXCLK);
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t = mode >> RT3883_GPIO_MODE_PCI_SHIFT;
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t &= RT3883_GPIO_MODE_PCI_MASK;
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if (t != RT3883_GPIO_MODE_PCI_GPIO)
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rt3883_gpio_reserve(RT3883_GPIO_PCI_AD0,
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RT3883_GPIO_PCI_AD31);
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t = mode >> RT3883_GPIO_MODE_LNA_A_SHIFT;
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t &= RT3883_GPIO_MODE_LNA_A_MASK;
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if (t != RT3883_GPIO_MODE_LNA_A_GPIO)
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rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_A0,
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RT3883_GPIO_LNA_PE_A2);
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t = mode >> RT3883_GPIO_MODE_LNA_G_SHIFT;
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t &= RT3883_GPIO_MODE_LNA_G_MASK;
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if (t != RT3883_GPIO_MODE_LNA_G_GPIO)
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rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_G0,
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RT3883_GPIO_LNA_PE_G2);
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}
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