84 lines
3 KiB
Diff
84 lines
3 KiB
Diff
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From 330916bb64ca043ad03993aa4041edc99f68cf8f Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 15 Sep 2016 17:52:17 +0100
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Subject: [PATCH] drm/vc4: Enable limited range RGB output with CEA modes.
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 28 ++++++++++++++++++++++++++--
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drivers/gpu/drm/vc4/vc4_regs.h | 9 ++++++++-
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2 files changed, 34 insertions(+), 3 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -285,6 +285,7 @@ static void vc4_hdmi_encoder_mode_set(st
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struct drm_display_mode *unadjusted_mode,
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struct drm_display_mode *mode)
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{
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+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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bool debug_dump_regs = false;
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@@ -300,6 +301,7 @@ static void vc4_hdmi_encoder_mode_set(st
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u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
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VC4_HDMI_VERTB_VBP));
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+ u32 csc_ctl;
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if (debug_dump_regs) {
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DRM_INFO("HDMI regs before:\n");
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@@ -338,9 +340,31 @@ static void vc4_hdmi_encoder_mode_set(st
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(vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
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(hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
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+ csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
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+ VC4_HD_CSC_CTL_ORDER);
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+
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+ if (vc4_encoder->hdmi_monitor && drm_match_cea_mode(mode) != 0) {
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+ /* Enable limited range RGB output. This matrix is:
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+ * [ 0 0 0.8594 16]
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+ * [ 0 0.8594 0 16]
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+ * [ 0.8594 0 0 16]
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+ * [ 0 0 0 1]
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+ */
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+ csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
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+ csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
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+ csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
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+ VC4_HD_CSC_CTL_MODE);
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+
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+ HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
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+ HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
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+ HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
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+ HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
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+ HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
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+ HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
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+ }
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+
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/* The RGB order applies even when CSC is disabled. */
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- HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
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- VC4_HD_CSC_CTL_ORDER));
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+ HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
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HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -530,10 +530,17 @@
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# define VC4_HD_CSC_CTL_MODE_SHIFT 2
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# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
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# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
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-# define VC4_HD_CSC_CTL_MODE_CUSTOM 2
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+# define VC4_HD_CSC_CTL_MODE_CUSTOM 3
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# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
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# define VC4_HD_CSC_CTL_ENABLE BIT(0)
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+#define VC4_HD_CSC_12_11 0x044
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+#define VC4_HD_CSC_14_13 0x048
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+#define VC4_HD_CSC_22_21 0x04c
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+#define VC4_HD_CSC_24_23 0x050
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+#define VC4_HD_CSC_32_31 0x054
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+#define VC4_HD_CSC_34_33 0x058
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+
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#define VC4_HD_FRAME_COUNT 0x068
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/* HVS display list information. */
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