2011-10-10 15:14:17 +00:00
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/******************************************************************************
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**
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** FILE NAME : ifxmips_atm_fw_regs_danube.h
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** PROJECT : UEIP
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** MODULES : ATM (ADSL)
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**
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** DATE : 1 AUG 2005
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** AUTHOR : Xu Liang
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** DESCRIPTION : ATM Driver (Firmware Registers)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 4 AUG 2005 Xu Liang Initiate Version
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** 23 OCT 2006 Xu Liang Add GPL header.
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** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
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*******************************************************************************/
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2010-12-12 22:57:16 +00:00
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#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H
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#define IFXMIPS_ATM_FW_REGS_DANUBE_H
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/*
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* Host-PPE Communication Data Address Mapping
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*/
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2011-10-10 15:14:17 +00:00
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#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001))
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2010-12-12 22:57:16 +00:00
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#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
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#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
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#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
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#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
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#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
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#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
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#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
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#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */
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#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20))
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2011-10-10 15:14:17 +00:00
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#define WRX_QUEUE_CONTEXT(i) ((struct wrx_queue_context*) SB_BUFFER(0x2504 + (i) * 20))
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2010-12-12 22:57:16 +00:00
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#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7))
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2011-10-10 15:14:17 +00:00
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#define WRX_DESC_CONTEXT(i) ((struct wrx_desc_context*) SB_BUFFER(0x2643 + (i) * 7))
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2010-12-12 22:57:16 +00:00
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#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i)))
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#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27))
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#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27))
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#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410))
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2011-10-10 15:14:17 +00:00
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#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX
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#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i)))
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#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i)))
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#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i)))
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#else
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#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2020 + (i)))
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#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2040 + (i)))
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#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2060 + (i)))
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#endif
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#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
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#define RETX_MODE_CFG ((volatile struct Retx_mode_cfg *) SB_BUFFER(0x2408))
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#define RETX_TSYNC_CFG ((volatile struct Retx_Tsync_cfg *) SB_BUFFER(0x2409))
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#define RETX_TD_CFG ((volatile struct Retx_Td_cfg *) SB_BUFFER(0x240A))
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#define RETX_MIB_TIMER_CFG ((volatile struct Retx_MIB_Timer_cfg *) SB_BUFFER(0x240B))
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#define RETX_PLAYOUT_BUFFER_BASE SB_BUFFER(0x240D)
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#define RETX_SERVICE_HEADER_CFG SB_BUFFER(0x240E)
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#define RETX_MASK_HEADER_CFG SB_BUFFER(0x240F)
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#define RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) PPE_REG_ADDR(0x0D78))
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#define BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AC))
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#define FIRST_BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AE))
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#define PB_BUFFER_USAGE SB_BUFFER(0x2100)
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#define DTU_STAT_INFO ((volatile struct DTU_stat_info *) SB_BUFFER(0x2180))
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#define DTU_VLD_STAT SB_BUFFER(0x2380)
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//=====================================================================
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// retx firmware mib, for debug purpose
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// address : 0x2388 - 0x238F
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// size : 8
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//=====================================================================
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#define URETX_RX_TOTAL_DTU SB_BUFFER(0x2388)
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#define URETX_RX_BAD_DTU SB_BUFFER(0x2389)
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#define URETX_RX_GOOD_DTU SB_BUFFER(0x238A)
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#define URETX_RX_CORRECTED_DTU SB_BUFFER(0x238B)
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#define URETX_RX_OUTOFDATE_DTU SB_BUFFER(0x238C)
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#define URETX_RX_DUPLICATE_DTU SB_BUFFER(0x238D)
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#define URETX_RX_TIMEOUT_DTU SB_BUFFER(0x238E)
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#define URETX_ALPHA_SWITCH_TO_HUNT_TIMES SB_BUFFER(0x238F)
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// cell counter for debug purpose
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#define WRX_BC0_CELL_NUM SB_BUFFER(0x23E0)
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#define WRX_BC0_DROP_CELL_NUM SB_BUFFER(0x23E1)
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#define WRX_BC0_NONRETX_CELL_NUM SB_BUFFER(0x23E2)
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#define WRX_BC0_RETX_CELL_NUM SB_BUFFER(0x23E3)
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#define WRX_BC0_OUTOFDATE_CELL_NUM SB_BUFFER(0x23E4)
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#define WRX_BC0_DIRECTUP_NUM SB_BUFFER(0x23E5)
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#define WRX_BC0_PBW_TOTAL_NUM SB_BUFFER(0x23E6)
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#define WRX_BC0_PBW_SUCC_NUM SB_BUFFER(0x23E7)
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#define WRX_BC0_PBW_FAIL_NUM SB_BUFFER(0x23E8)
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#define WRX_BC1_CELL_NUM SB_BUFFER(0x23E9)
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// debug info (interface)
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#define DBG_DTU_INTF_WRPTR SB_BUFFER(0x2390)
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#define DBG_INTF_FCW_DUP_CNT SB_BUFFER(0x2391)
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#define DBG_INTF_SID_CHANGE_IN_DTU_CNT SB_BUFFER(0x2392)
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#define DBG_INTF_LCW_DUP_CNT SB_BUFFER(0x2393)
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#define DBG_RFBI_DONE_INT_CNT SB_BUFFER(0x2394)
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#define DBG_DREG_BEG_END SB_BUFFER(0x2395)
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#define DBG_RFBI_BC0_INVALID_CNT SB_BUFFER(0x2396)
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#define DBG_RFBI_LAST_T SB_BUFFER(0x2397)
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#define DBG_RFBI_INTV0 SB_BUFFER(0x23EE)
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#define DBG_RFBI_INTV1 SB_BUFFER(0x23EF)
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#define DBG_INTF_INFO(i) ((volatile struct Retx_adsl_ppe_intf_rec *) SB_BUFFER(0x23F0 + i))
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// Internal status
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#define URetx_curr_time SB_BUFFER(0x2398)
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#define URetx_sec_counter SB_BUFFER(0x2399)
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#define RxCURR_EFB SB_BUFFER(0x239A)
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#define RxDTURetransmittedCNT SB_BUFFER(0x239B)
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//=====================================================================
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// standardized MIB counter
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// address : 0x239C - 0x239F
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// size : 4
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//=====================================================================
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#define RxLastEFBCNT SB_BUFFER(0x239C)
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#define RxDTUCorrectedCNT SB_BUFFER(0x239D)
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#define RxDTUCorruptedCNT SB_BUFFER(0x239E)
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#define RxRetxDTUUncorrectedCNT SB_BUFFER(0x239F)
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//=====================================================================
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// General URetx Context
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// address : 0x23A0 - 0x23AF
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// size : 16
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//=====================================================================
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#define NEXT_DTU_SID_OUT SB_BUFFER(0x23A0)
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#define LAST_DTU_SID_IN SB_BUFFER(0x23A1)
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#define NEXT_CELL_SID_OUT SB_BUFFER(0x23A2)
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#define ISR_CELL_ID SB_BUFFER(0x23A3)
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#define PB_CELL_SEARCH_IDX SB_BUFFER(0x23A4)
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#define PB_READ_PEND_FLAG SB_BUFFER(0x23A5)
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#define RFBI_FIRST_CW SB_BUFFER(0x23A6)
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#define RFBI_BAD_CW SB_BUFFER(0x23A7)
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#define RFBI_INVALID_CW SB_BUFFER(0x23A8)
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#define RFBI_RETX_CW SB_BUFFER(0x23A9)
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#define RFBI_CHK_DTU_STATUS SB_BUFFER(0x23AA)
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//=====================================================================
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// per PVC counter for RX error_pdu and correct_pdu
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// address : 0x23B0 - 0x23CF
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// size : 32
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//=====================================================================
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#define WRX_PER_PVC_CORRECT_PDU_BASE SB_BUFFER(0x23B0)
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#define WRX_PER_PVC_ERROR_PDU_BASE SB_BUFFER(0x23C0)
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#define __WRXCTXT_L2_RdPtr(i) SB_BUFFER(0x2422 + (i))
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#define __WRXCTXT_L2Pages(i) SB_BUFFER(0x2424 + (i))
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#define __WTXCTXT_TC_WRPTR(i) SB_BUFFER(0x2450 + (i))
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#define __WRXCTXT_PortState(i) SB_BUFFER(0x242A + (i))
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#endif
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2010-12-12 22:57:16 +00:00
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#endif // IFXMIPS_ATM_FW_REGS_DANUBE_H
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