2016-06-08 09:59:37 +00:00
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From b7c76f75bc8e373d185a222bf7fa0ceb5f9d6d0a Mon Sep 17 00:00:00 2001
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2016-04-24 11:03:39 +00:00
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From: Eric Anholt <eric@anholt.net>
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Date: Tue, 16 Feb 2016 10:24:08 -0800
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2016-06-08 09:59:37 +00:00
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Subject: [PATCH 292/381] drm/vc4: Initialize scaler DISPBKGND on modeset.
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2016-04-24 11:03:39 +00:00
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We weren't updating the interlaced bit, so we'd scan out incorrectly
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if the firmware had brought up the TV encoder and we were switching to
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HDMI.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 6a609209865247cc748e90158c99f374f79b494c)
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 6 ++++++
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drivers/gpu/drm/vc4/vc4_regs.h | 14 ++++++++++++++
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2 files changed, 20 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -188,6 +188,8 @@ static int vc4_get_clock_select(struct d
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static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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+ struct drm_device *dev = crtc->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_crtc_state *state = crtc->state;
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struct drm_display_mode *mode = &state->adjusted_mode;
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@@ -256,6 +258,10 @@ static void vc4_crtc_mode_set_nofb(struc
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PV_CONTROL_FIFO_CLR |
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PV_CONTROL_EN);
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+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
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+ SCALER_DISPBKGND_AUTOHS |
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+ (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
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+
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
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vc4_crtc_dump_regs(vc4_crtc);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -350,6 +350,17 @@
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# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
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#define SCALER_DISPBKGND0 0x00000044
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+# define SCALER_DISPBKGND_AUTOHS BIT(31)
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+# define SCALER_DISPBKGND_INTERLACE BIT(30)
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+# define SCALER_DISPBKGND_GAMMA BIT(29)
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+# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
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+# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
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+/* Enables filling the scaler line with the RGB value in the low 24
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+ * bits before compositing. Costs cycles, so should be skipped if
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+ * opaque display planes will cover everything.
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+ */
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+# define SCALER_DISPBKGND_FILL BIT(24)
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+
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#define SCALER_DISPSTAT0 0x00000048
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#define SCALER_DISPBASE0 0x0000004c
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# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
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@@ -362,6 +373,9 @@
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# define SCALER_DISPSTATX_EMPTY BIT(28)
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#define SCALER_DISPCTRL1 0x00000050
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#define SCALER_DISPBKGND1 0x00000054
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+#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
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+ (x) * (SCALER_DISPBKGND1 - \
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+ SCALER_DISPBKGND0))
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#define SCALER_DISPSTAT1 0x00000058
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#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
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(x) * (SCALER_DISPSTAT1 - \
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