2015-04-07 22:06:17 +00:00
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--- a/drivers/ssb/driver_pcicore.c
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+++ b/drivers/ssb/driver_pcicore.c
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2015-06-01 06:11:26 +00:00
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@@ -357,6 +357,16 @@ static void ssb_pcicore_init_hostmode(st
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2015-04-07 22:06:17 +00:00
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
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SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
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+ /*
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+ * Accessing PCI config without a proper delay after devices reset (not
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2015-06-01 06:11:26 +00:00
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+ * GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704).
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2015-04-07 22:06:17 +00:00
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+ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it
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+ * completely. Flushing all writes was also tested but with no luck.
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2015-06-01 06:11:26 +00:00
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+ * The same problem was reported for WRT350N v1 (BCM4705), so we just
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+ * sleep here unconditionally.
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2015-04-07 22:06:17 +00:00
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+ */
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2015-06-01 06:11:26 +00:00
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+ usleep_range(1000, 2000);
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2015-04-07 22:06:17 +00:00
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+
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/* Enable PCI bridge BAR0 prefetch and burst */
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val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -1135,6 +1135,8 @@ static u32 ssb_tmslow_reject_bitmask(str
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case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
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case SSB_IDLOW_SSBREV_27: /* same here */
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return SSB_TMSLOW_REJECT; /* this is a guess */
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+ case SSB_IDLOW_SSBREV:
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+ break;
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default:
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WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
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}
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