2014-08-11 11:36:53 +00:00
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm6338";
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2014-08-11 11:37:01 +00:00
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aliases {
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pflash = &pflash;
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};
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2014-08-11 11:36:53 +00:00
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cpus {
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2014-12-01 00:51:53 +00:00
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#address-cells = <1>;
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#size-cells = <0>;
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2014-08-11 11:36:53 +00:00
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cpu@0 {
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compatible = "brcm,bmips3300", "mips,mips4Kc";
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2014-12-01 00:51:53 +00:00
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device_type = "cpu";
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reg = <0>;
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2014-08-11 11:36:53 +00:00
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};
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};
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2014-12-01 00:52:07 +00:00
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cpu_intc: interrupt-controller {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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2014-08-11 11:36:53 +00:00
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memory { device_type = "memory"; reg = <0 0>; };
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2014-08-11 11:37:01 +00:00
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pflash: nor@1fc00000 {
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compatible = "cfi-flash";
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reg = <0x1fc00000 0x400000>;
|
2014-08-21 11:27:56 +00:00
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bank-width = <2>;
|
2014-08-11 11:37:01 +00:00
|
|
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#address-cells = <1>;
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|
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#size-cells = <1>;
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status = "disabled";
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};
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|
2014-08-11 11:36:53 +00:00
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|
|
ubus@fff00000 {
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|
|
#address-cells = <1>;
|
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|
|
#size-cells = <1>;
|
2014-12-01 00:51:56 +00:00
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ranges;
|
2014-08-11 11:36:53 +00:00
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|
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compatible = "simple-bus";
|
2014-12-01 00:52:07 +00:00
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periph_intc: interrupt-controller@fffe000c {
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|
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compatible = "brcm,bcm6345-l2-intc";
|
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|
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reg = <0xfffe000c 0x8>;
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|
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interrupt-controller;
|
|
|
|
#interrupt-cells = <1>;
|
|
|
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|
|
|
|
interrupt-parent = <&cpu_intc>;
|
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|
|
interrupts = <2>;
|
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|
|
};
|
|
|
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|
|
|
ext_intc: interrupt-controller@fffe0014 {
|
|
|
|
compatible = "brcm,bcm6345-ext-intc";
|
|
|
|
reg = <0xfffe0014 0x4>;
|
|
|
|
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
|
|
|
interrupt-parent = <&cpu_intc>;
|
|
|
|
interrupts = <3>, <4>, <5>, <6>;
|
|
|
|
};
|
2014-08-11 11:36:53 +00:00
|
|
|
};
|
|
|
|
};
|