33 lines
1,005 B
Diff
33 lines
1,005 B
Diff
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From 367c16da9255dacf6440f3c72c01c197cfb1bbe8 Mon Sep 17 00:00:00 2001
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From: Sumit Garg <sumit.garg@nxp.com>
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Date: Wed, 11 May 2016 12:44:35 -0400
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Subject: [PATCH 30/93] ARMv8: Enable CPUECTLR.SMPEN for data coherency
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Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
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The SMPEN bit should be set before enabling the data cache. If not
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enabled, the cache is not coherent with other cores and data
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corruption could occur. It also enables core level cache snooping.
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Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
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---
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arch/arm/cpu/armv8/start.S | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
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index 235213f..9703f6b 100644
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--- a/arch/arm/cpu/armv8/start.S
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+++ b/arch/arm/cpu/armv8/start.S
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@@ -70,6 +70,9 @@ reset:
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mov x0, #3 << 20
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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+ /* Enalbe SMPEN bit */
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+ mov x0, #0x40
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+ msr s3_1_c15_c2_1, x0
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/* Apply ARM core specific erratas */
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bl apply_core_errata
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--
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1.7.9.5
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