32 lines
1 KiB
Diff
32 lines
1 KiB
Diff
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From: Felix Fietkau <nbd@nbd.name>
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Date: Sat, 14 May 2016 20:20:04 +0200
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Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer
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SoCs
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AR913x, AR724x and AR933x are the only SoCs where the
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ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
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Invert the logic to make the code compatible with AR95xx
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void)
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{
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ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
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AR71XX_DDR_CTRL_SIZE);
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- if (soc_is_ar71xx() || soc_is_ar934x()) {
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- ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
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- ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
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- } else {
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+ if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
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ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
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ath79_ddr_pci_win_base = 0;
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+ } else {
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+ ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
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+ ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
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}
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}
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EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
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