54 lines
1.9 KiB
Diff
54 lines
1.9 KiB
Diff
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From 066320dd0643e66bc5afe0d0984e77b2e938a6f4 Mon Sep 17 00:00:00 2001
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From: Minghuan Lian <Minghuan.Lian@nxp.com>
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Date: Wed, 23 Mar 2016 19:08:19 +0800
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Subject: [PATCH 03/13] dt/bindings: Add bindings for Layerscape SCFG MSI
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Cherry-pick upstream patch.
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Some Layerscape SoCs use a simple MSI controller implementation.
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It contains only two SCFG register to trigger and describe a
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group 32 MSI interrupts. The patch adds bindings to describe
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the controller.
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Acked-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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.../interrupt-controller/fsl,ls-scfg-msi.txt | 30 ++++++++++++++++++++++
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1 file changed, 30 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
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@@ -0,0 +1,30 @@
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+* Freescale Layerscape SCFG PCIe MSI controller
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+
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+Required properties:
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+
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+- compatible: should be "fsl,<soc-name>-msi" to identify
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+ Layerscape PCIe MSI controller block such as:
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+ "fsl,1s1021a-msi"
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+ "fsl,1s1043a-msi"
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+- msi-controller: indicates that this is a PCIe MSI controller node
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+- reg: physical base address of the controller and length of memory mapped.
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+- interrupts: an interrupt to the parent interrupt controller.
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+
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+Optional properties:
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+- interrupt-parent: the phandle to the parent interrupt controller.
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+
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+This interrupt controller hardware is a second level interrupt controller that
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+is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
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+platforms. If interrupt-parent is not provided, the default parent interrupt
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+controller will be used.
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+Each PCIe node needs to have property msi-parent that points to
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+MSI controller node
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+
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+Examples:
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+
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+ msi1: msi-controller@1571000 {
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+ compatible = "fsl,1s1043a-msi";
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+ reg = <0x0 0x1571000 0x0 0x8>,
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+ msi-controller;
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+ interrupts = <0 116 0x4>;
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+ };
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