44 lines
1.5 KiB
Diff
44 lines
1.5 KiB
Diff
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From 2083f21dc65df8ce4fd887acd815551058b23e3e Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 11:39:17 +0000
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Subject: [PATCH 256/304] clk: bcm2835: pll_off should only update
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CM_PLL_ANARST
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bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
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register, which may lose the other bits that are currently set by the
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clock dividers.
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It also now locks during the read/modify/write cycle of both
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registers.
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Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
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audio domain clocks")
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06)
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---
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drivers/clk/bcm/clk-bcm2835.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -913,8 +913,14 @@ static void bcm2835_pll_off(struct clk_h
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struct bcm2835_cprman *cprman = pll->cprman;
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const struct bcm2835_pll_data *data = pll->data;
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- cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
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- cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);
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+ spin_lock(&cprman->regs_lock);
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+ cprman_write(cprman, data->cm_ctrl_reg,
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+ cprman_read(cprman, data->cm_ctrl_reg) |
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+ CM_PLL_ANARST);
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+ cprman_write(cprman, data->a2w_ctrl_reg,
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+ cprman_read(cprman, data->a2w_ctrl_reg) |
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+ A2W_PLL_CTRL_PWRDN);
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+ spin_unlock(&cprman->regs_lock);
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}
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static int bcm2835_pll_on(struct clk_hw *hw)
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