openwrtv4/target/linux/brcm63xx/patches-3.10/067-MIPS-BMIPS-add-a-smp-ops-registration-helper.patch

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From 0b135a3e8f344061ed0aa66e2514627dd7aa946f Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 23 Jun 2013 14:04:51 +0200
Subject: [PATCH V2 08/13] MIPS: BMIPS: add a smp ops registration helper
Add a helper similar to the generic register_XXX_smp_ops() for bmips.
Register SMP UP ops in case of BMIPS32/3300.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
V1 -> V2:
* use SMP_UP (ops) in case of BMIPS32_3300
arch/mips/Kconfig | 1 +
arch/mips/bcm63xx/prom.c | 2 +-
arch/mips/include/asm/bmips.h | 26 ++++++++++++++++++++++++++
3 files changed, 28 insertions(+), 1 deletion(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1551,6 +1551,7 @@ config CPU_LOONGSON1
select CPU_SUPPORTS_HIGHMEM
config CPU_BMIPS32_3300
+ select SMP_UP if SMP
bool
config CPU_BMIPS4350
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -61,7 +61,7 @@ void __init prom_init(void)
if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
/* set up SMP */
- register_smp_ops(&bmips43xx_smp_ops);
+ register_bmips_smp_ops();
/*
* BCM6328 might not have its second CPU enabled, while BCM3368
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -46,9 +46,35 @@
#include <linux/cpumask.h>
#include <asm/r4kcache.h>
+#include <asm/smp-ops.h>
extern struct plat_smp_ops bmips43xx_smp_ops;
extern struct plat_smp_ops bmips5000_smp_ops;
+
+static inline int register_bmips_smp_ops(void)
+{
+#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
+ switch (current_cpu_type()) {
+ case CPU_BMIPS32:
+ case CPU_BMIPS3300:
+ return register_up_smp_ops();
+ case CPU_BMIPS4350:
+ case CPU_BMIPS4380:
+ register_smp_ops(&bmips43xx_smp_ops);
+ break;
+ case CPU_BMIPS5000:
+ register_smp_ops(&bmips5000_smp_ops);
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ return 0;
+#else
+ return -ENODEV;
+#endif
+}
+
extern char bmips_reset_nmi_vec;
extern char bmips_reset_nmi_vec_end;
extern char bmips_smp_movevec;