72b58f2eb1
This is the oxnas target previously developed at http://gitorious.org/openwrt-oxnas Basically, this consolidates the changes and addtionas from http://github.org/kref/linux-oxnas into a new OpenWrt hardware target 'oxnas' adding support for PLX Technology NAS7820/NAS7821/NAS7825/... formally known as Oxford Semiconductor OXE810SE/OXE815/OX820/... For now there are 4 supported boards: Cloud Engines Pogoplug V3 (without PCIe) fully supported Cloud Engines Pogoplug Pro (with PCIe) fully supported MitraStar STG-212 aka ZyXEL NSA-212, aka Medion Akoya P89625 / P89636 / P89626 / P89630, aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587 fully supported, see http://wiki.openwrt.org/toh/medion/md86587 Shuttle KD-20 partially supported (S-ATA driver lacks support for 2nd port) Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43388
107 lines
2.5 KiB
C
107 lines
2.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <mach/hardware.h>
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static int ox820_reset_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
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writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
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return 0;
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}
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static int ox820_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
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return 0;
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}
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static int ox820_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
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return 0;
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}
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static struct reset_control_ops ox820_reset_ops = {
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.reset = ox820_reset_reset,
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.assert = ox820_reset_assert,
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.deassert = ox820_reset_deassert,
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};
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static const struct of_device_id ox820_reset_dt_ids[] = {
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{ .compatible = "plxtech,nas782x-reset", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, ox820_reset_dt_ids);
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struct reset_controller_dev rcdev;
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static int ox820_reset_probe(struct platform_device *pdev)
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{
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struct reset_controller_dev *rcdev;
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rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
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if (!rcdev)
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return -ENOMEM;
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/* note: reset controller is statically mapped */
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rcdev->owner = THIS_MODULE;
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rcdev->nr_resets = 32;
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rcdev->ops = &ox820_reset_ops;
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rcdev->of_node = pdev->dev.of_node;
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reset_controller_register(rcdev);
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platform_set_drvdata(pdev, rcdev);
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return 0;
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}
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static int ox820_reset_remove(struct platform_device *pdev)
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{
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struct reset_controller_dev *rcdev = platform_get_drvdata(pdev);
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reset_controller_unregister(rcdev);
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return 0;
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}
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static struct platform_driver ox820_reset_driver = {
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.probe = ox820_reset_probe,
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.remove = ox820_reset_remove,
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.driver = {
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.name = "ox820-reset",
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.owner = THIS_MODULE,
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.of_match_table = ox820_reset_dt_ids,
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},
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};
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static int __init ox820_reset_init(void)
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{
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return platform_driver_probe(&ox820_reset_driver,
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ox820_reset_probe);
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}
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/*
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* reset controller does not support probe deferral, so it has to be
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* initialized before any user, in particular, PCIE uses subsys_initcall.
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*/
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arch_initcall(ox820_reset_init);
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MODULE_AUTHOR("Ma Haijun");
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MODULE_LICENSE("GPL");
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