ad907e1c03
Add support for NXP layerscape ls1046ardb 64b/32b Dev board. LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot * USB 3.0: one super speed USB 3.0 type A port, one Micro-AB port * UART: supports two UARTs up to 115200 bps for console Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
75 lines
2.2 KiB
Diff
75 lines
2.2 KiB
Diff
From 4fe33d4f4dc608fc5013390db58df06723282d01 Mon Sep 17 00:00:00 2001
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From: Mingkai Hu <mingkai.hu@nxp.com>
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Date: Thu, 2 Jun 2016 11:15:58 +0800
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Subject: [PATCH 129/141] clk: qoriq: add ls1046a support
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Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
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Integated-by: Yutang Jiang <yutang.jiang@nxp.com>
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---
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drivers/clk/clk-qoriq.c | 41 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 41 insertions(+)
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--- a/drivers/clk/clk-qoriq.c
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+++ b/drivers/clk/clk-qoriq.c
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@@ -275,6 +275,31 @@ static const struct clockgen_muxinfo ls1
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},
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};
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+static const struct clockgen_muxinfo ls1046a_hwa1 = {
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+ {
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+ {},
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+ {},
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+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
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+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
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+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
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+ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
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+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
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+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
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+ },
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+};
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+
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+static const struct clockgen_muxinfo ls1046a_hwa2 = {
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+ {
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+ {},
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+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
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+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
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+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
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+ {},
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+ {},
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+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
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+ },
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+};
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+
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static const struct clockgen_muxinfo t1023_hwa1 = {
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{
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{},
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@@ -508,6 +533,21 @@ static const struct clockgen_chipinfo ch
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.flags = CG_PLL_8BIT,
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},
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{
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+ .compat = "fsl,ls1046a-clockgen",
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+ .init_periph = t2080_init_periph,
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+ .cmux_groups = {
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+ &t1040_cmux
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+ },
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+ .hwaccel = {
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+ &ls1046a_hwa1, &ls1046a_hwa2
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+ },
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+ .cmux_to_group = {
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+ 0, -1
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+ },
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+ .pll_mask = 0x07,
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+ .flags = CG_PLL_8BIT,
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+ },
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+ {
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.compat = "fsl,ls2080a-clockgen",
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.cmux_groups = {
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&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
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@@ -1285,6 +1325,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qo
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CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
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+CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
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