f9b8328d79
Add the ranges property to the PCI bridges where missing. Add the unit address to PCI bridge where missing. Rework the complete rt3883 pci node. Drop the PCI unit nodes from the dtsi. They are not used by any dts file and should be rather in the dts than in the SoC dtsi. Express the PCI-PCI bridge in a clean devicetree syntax. The ralink,pci-slot isn't used by any driver, drop it. Move the pci interrupt controller out of the pci node. It doesn't share the same reg and therefore should be an independent/SoC child node. Move the pci related rt3883 pinctrl setting to the dtsi instead of defining the very same for each rt3883 board. If the device_type property is used for PCI units, the unit is treated as pci bridge which it isn't. Drop it for PCI units. Reference pci-bridges or the pci node defined in the dtsi instead of recreating the whole node hierarchy. It allows to change the referenced node in the dtsi without the need to touch all dts. Fix the PCI(e) wireless unit addresses. All our PCI(e) wireless chips are the first device on the bus. The unit address has to be the bus address instead of the PCI vendor/device id. Signed-off-by: Mathias Kresin <dev@kresin.me>
579 lines
9.9 KiB
Text
579 lines
9.9 KiB
Text
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,mtk7620a-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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reg = <0>;
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};
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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cpuintc: cpuintc {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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aliases {
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spi0 = &spi0;
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spi1 = &spi1;
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serial0 = &uartlite;
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};
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palmbus: palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: sysc@0 {
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compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
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reg = <0x0 0x100>;
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};
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timer: timer@100 {
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compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
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reg = <0x100 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <1>;
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};
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watchdog: watchdog@120 {
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compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
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reg = <0x120 0x10>;
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resets = <&rstctrl 8>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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interrupts = <1>;
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};
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intc: intc@200 {
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compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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resets = <&rstctrl 19>;
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reset-names = "intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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memc: memc@300 {
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compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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resets = <&rstctrl 20>;
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reset-names = "mc";
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interrupt-parent = <&intc>;
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interrupts = <3>;
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};
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uart: uart@500 {
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compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0x500 0x100>;
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resets = <&rstctrl 12>;
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reset-names = "uart";
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interrupt-parent = <&intc>;
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interrupts = <5>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio0: gpio@600 {
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compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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reg = <0x600 0x34>;
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resets = <&rstctrl 13>;
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reset-names = "pio";
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <0>;
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ralink,nr-gpio = <24>;
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ralink,register-map = [ 00 04 08 0c
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20 24 28 2c
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30 34 ];
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};
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gpio1: gpio@638 {
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compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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reg = <0x638 0x24>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <24>;
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ralink,nr-gpio = <16>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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gpio2: gpio@660 {
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compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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reg = <0x660 0x24>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <40>;
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ralink,nr-gpio = <32>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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gpio3: gpio@688 {
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compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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reg = <0x688 0x24>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <72>;
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ralink,nr-gpio = <1>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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i2c: i2c@900 {
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compatible = "ralink,rt2880-i2c";
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reg = <0x900 0x100>;
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resets = <&rstctrl 16>;
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reset-names = "i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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};
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i2s: i2s@a00 {
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compatible = "mediatek,mt7620-i2s";
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reg = <0xa00 0x100>;
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resets = <&rstctrl 17>;
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reset-names = "i2s";
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interrupt-parent = <&intc>;
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interrupts = <10>;
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txdma-req = <2>;
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rxdma-req = <3>;
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dmas = <&gdma 4>,
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<&gdma 6>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi0: spi@b00 {
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compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
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reg = <0xb00 0x40>;
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resets = <&rstctrl 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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};
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spi1: spi@b40 {
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compatible = "ralink,rt2880-spi";
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reg = <0xb40 0x60>;
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resets = <&rstctrl 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&spi_cs1>;
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};
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uartlite: uartlite@c00 {
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compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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resets = <&rstctrl 19>;
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reset-names = "uartl";
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interrupt-parent = <&intc>;
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interrupts = <12>;
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reg-shift = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uartlite_pins>;
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};
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systick: systick@d00 {
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compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
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reg = <0xd00 0x10>;
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resets = <&rstctrl 28>;
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reset-names = "intc";
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interrupt-parent = <&cpuintc>;
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interrupts = <7>;
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};
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pcm: pcm@2000 {
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compatible = "ralink,mt7620a-pcm";
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reg = <0x2000 0x800>;
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resets = <&rstctrl 11>;
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reset-names = "pcm";
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interrupt-parent = <&intc>;
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interrupts = <4>;
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status = "disabled";
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};
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gdma: gdma@2800 {
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compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
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reg = <0x2800 0x800>;
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resets = <&rstctrl 14>;
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reset-names = "dma";
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interrupt-parent = <&intc>;
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interrupts = <7>;
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#dma-cells = <1>;
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#dma-channels = <16>;
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#dma-requests = <16>;
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status = "disabled";
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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};
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pcm_i2s_pins: pcm_i2s {
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pcm_i2s {
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ralink,group = "uartf";
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ralink,function = "pcm i2s";
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};
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};
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uartf_gpio_pins: uartf_gpio {
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uartf_gpio {
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ralink,group = "uartf";
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ralink,function = "gpio uartf";
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};
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};
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gpio_i2s_pins: gpio_i2s {
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gpio_i2s {
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ralink,group = "uartf";
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ralink,function = "gpio i2s";
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};
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};
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spi_pins: spi {
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spi {
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ralink,group = "spi";
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ralink,function = "spi";
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};
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};
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spi_cs1: spi1 {
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spi1 {
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ralink,group = "spi_cs1";
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ralink,function = "spi_cs1";
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};
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};
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i2c_pins: i2c {
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i2c {
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ralink,group = "i2c";
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ralink,function = "i2c";
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};
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};
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uartlite_pins: uartlite {
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uart {
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ralink,group = "uartlite";
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ralink,function = "uartlite";
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};
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};
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mdio_pins: mdio {
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mdio {
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ralink,group = "mdio";
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ralink,function = "mdio";
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};
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};
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mdio_refclk_pins: mdio_refclk {
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mdio_refclk {
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ralink,group = "mdio";
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ralink,function = "refclk";
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};
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};
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ephy_pins: ephy {
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ephy {
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ralink,group = "ephy";
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ralink,function = "ephy";
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};
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};
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wled_pins: wled {
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wled {
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ralink,group = "wled";
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ralink,function = "wled";
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};
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};
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rgmii1_pins: rgmii1 {
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rgmii1 {
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ralink,group = "rgmii1";
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ralink,function = "rgmii1";
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};
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};
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rgmii2_pins: rgmii2 {
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rgmii2 {
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ralink,group = "rgmii2";
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ralink,function = "rgmii2";
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};
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};
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pcie_pins: pcie {
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pcie {
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ralink,group = "pcie";
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ralink,function = "pcie rst";
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};
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};
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pa_pins: pa {
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pa {
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ralink,group = "pa";
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ralink,function = "pa";
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};
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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clkctrl: clkctrl {
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compatible = "ralink,rt2880-clock";
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#clock-cells = <1>;
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};
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usbphy: usbphy {
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compatible = "mediatek,mt7620-usbphy";
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#phy-cells = <0>;
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ralink,sysctl = <&sysc>;
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resets = <&rstctrl 22 &rstctrl 25>;
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reset-names = "host", "device";
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clocks = <&clkctrl 22 &clkctrl 25>;
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clock-names = "host", "device";
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};
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ethernet: ethernet@10100000 {
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compatible = "mediatek,mt7620-eth";
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reg = <0x10100000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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resets = <&rstctrl 21 &rstctrl 23>;
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reset-names = "fe", "esw";
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mediatek,switch = <&gsw>;
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port@4 {
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compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
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reg = <4>;
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status = "disabled";
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};
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port@5 {
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compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
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reg = <5>;
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status = "disabled";
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsw: gsw@10110000 {
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compatible = "mediatek,mt7620-gsw";
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reg = <0x10110000 0x8000>;
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resets = <&rstctrl 23>;
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reset-names = "esw";
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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sdhci: sdhci@10130000 {
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compatible = "ralink,mt7620-sdhci";
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reg = <0x10130000 0x4000>;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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status = "disabled";
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};
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ehci: ehci@101c0000 {
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compatible = "generic-ehci";
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reg = <0x101c0000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <18>;
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phys = <&usbphy>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci: ohci@101c1000 {
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compatible = "generic-ohci";
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reg = <0x101c1000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <18>;
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phys = <&usbphy>;
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phy-names = "usb";
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status = "disabled";
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};
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pcie: pcie@10140000 {
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compatible = "mediatek,mt7620-pci";
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reg = <0x10140000 0x100
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0x10142000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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resets = <&rstctrl 26>;
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reset-names = "pcie0";
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clocks = <&clkctrl 26>;
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clock-names = "pcie0";
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
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>;
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status = "disabled";
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pcie0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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};
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wmac: wmac@10180000 {
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compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
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reg = <0x10180000 0x40000>;
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|
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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ralink,eeprom = "soc_wmac.eeprom";
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};
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};
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