1db4135e32
Adds preliminary kernel 4.9 support for this target. - Refreshed/Updated all patches Added 3 new patches: - 093 --> Add virtual PCI MMIO mapping - 230 --> Remove deprecated code - 240 --> Rework AT24 eeprom code to use the new NVMEM API Compiled & tested on cns3xxx (gw2388) Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
--- a/arch/arm/mach-cns3xxx/Kconfig
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+++ b/arch/arm/mach-cns3xxx/Kconfig
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@@ -5,6 +5,7 @@ menuconfig ARCH_CNS3XXX
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD
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select HAVE_SMP
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+ select FIQ
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help
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Support for Cavium Networks CNS3XXX platform.
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o
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cns3xxx-$(CONFIG_ATAGS) += devices.o
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cns3xxx-$(CONFIG_PCI) += pcie.o
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cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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-cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
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+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
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cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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--- a/arch/arm/mach-cns3xxx/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
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@@ -261,6 +261,7 @@
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#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
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#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
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+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
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/*
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* Power management and clock control
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*/
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -856,7 +856,7 @@ config VDSO
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config DMA_CACHE_RWFO
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bool "Enable read/write for ownership DMA cache maintenance"
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- depends on CPU_V6K && SMP
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+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
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default y
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help
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The Snoop Control Unit on ARM11MPCore does not detect the
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