204 lines
4.5 KiB
Diff
204 lines
4.5 KiB
Diff
From 9c83b58b49f88a48565fad6acea921a0ae222856 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 17:50:05 +0100
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Subject: [PATCH 112/121] MIPS: add MT7620 dts files
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Adds the dtsi file for MT7620 SoC. This is the latest and greatest SoC shipped
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by Mediatek.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/Kconfig | 4 +
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arch/mips/ralink/dts/Makefile | 1 +
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arch/mips/ralink/dts/mt7620.dtsi | 138 ++++++++++++++++++++++++++++++++++
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arch/mips/ralink/dts/mt7620_eval.dts | 22 ++++++
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4 files changed, 165 insertions(+)
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create mode 100644 arch/mips/ralink/dts/mt7620.dtsi
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create mode 100644 arch/mips/ralink/dts/mt7620_eval.dts
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -46,6 +46,10 @@ choice
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bool "RT3883 eval kit"
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depends on SOC_RT3883
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+ config DTB_MT7620_EVAL
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+ bool "MT7620 eval kit"
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+ depends on SOC_MT7620
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+
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endchoice
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endif
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--- a/arch/mips/ralink/dts/Makefile
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+++ b/arch/mips/ralink/dts/Makefile
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@@ -1,3 +1,4 @@
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obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
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obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
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obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
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+obj-$(CONFIG_DTB_MT7620_EVAL) := mt7620_eval.dtb.o
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--- /dev/null
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+++ b/arch/mips/ralink/dts/mt7620.dtsi
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@@ -0,0 +1,138 @@
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc";
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+
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+ cpus {
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+ cpu@0 {
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+ compatible = "mips,mips24KEc";
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+ };
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyS0,57600 init=/init";
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+ };
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+
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+ cpuintc: cpuintc@0 {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ compatible = "mti,cpu-interrupt-controller";
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+ };
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+
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+ palmbus@10000000 {
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+ compatible = "palmbus";
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+ reg = <0x10000000 0x200000>;
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+ ranges = <0x0 0x10000000 0x1FFFFF>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ sysc@0 {
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+ compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc";
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+ reg = <0x0 0x100>;
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+ };
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+
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+ timer@100 {
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+ compatible = "ralink,mt7620-timer", "ralink,rt2880-timer";
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+ reg = <0x100 0x20>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+
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+ status = "disabled";
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+ };
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+
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+ watchdog@120 {
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+ compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt";
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+ reg = <0x120 0x10>;
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+ };
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+
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+ intc: intc@200 {
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+ compatible = "ralink,mt7620-intc", "ralink,rt2880-intc";
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+ reg = <0x200 0x100>;
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+
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <2>;
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+ };
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+
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+ memc@300 {
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+ compatible = "ralink,mt7620-memc", "ralink,rt3050-memc";
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+ reg = <0x300 0x100>;
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+ };
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+
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+ gpio0: gpio@600 {
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+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
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+ reg = <0x600 0x34>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+ };
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+
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+ gpio1: gpio@638 {
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+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
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+ reg = <0x638 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,num-gpios = <16>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+ };
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+
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+ gpio2: gpio@660 {
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+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
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+ reg = <0x660 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,num-gpios = <32>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+ };
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+
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+ gpio3: gpio@688 {
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+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
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+ reg = <0x688 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,num-gpios = <1>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+ };
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+
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+ spi@b00 {
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+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
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+ reg = <0xb00 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ status = "disabled";
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+ };
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+
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+ uartlite@c00 {
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+ compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a";
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+ reg = <0xc00 0x100>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <12>;
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+
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+ reg-shift = <2>;
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/mips/ralink/dts/mt7620_eval.dts
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@@ -0,0 +1,22 @@
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+/dts-v1/;
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+
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+/include/ "mt7620.dtsi"
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
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+ model = "Ralink MT7620 evaluation board";
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+
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+ memory@0 {
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+ reg = <0x0 0x4000000>;
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+ };
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+
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+ palmbus@10000000 {
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+ sysc@0 {
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+ ralink,pinmmux = "uartlite", "spi";
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+ ralink,uartmux = "gpio";
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+ ralink,wdtmux = <0>;
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+ };
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+ };
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+};
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