3b88f74bbe
This backports some more patches from kernel 4.11 adding more devices to the device tree of the A64 SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
69 lines
2.2 KiB
Diff
69 lines
2.2 KiB
Diff
From f3dff3478a8a7b09f9a92023955a151584658893 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Thu, 6 Oct 2016 02:25:22 +0100
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Subject: arm64: allwinner: a64: Add MMC nodes
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The A64 has 3 MMC controllers, one of them being especially targeted to
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eMMC. Among other things, it has a data strobe signal and a 8 bits data
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width.
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The two other are more usual controllers that will have a 4 bits width at
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most and no data strobe signal, which limits it to more usual SD or MMC
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peripherals.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
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Acked-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 +++++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -121,6 +121,45 @@
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#size-cells = <1>;
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ranges;
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+ mmc0: mmc@1c0f000 {
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+ compatible = "allwinner,sun50i-a64-mmc";
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+ reg = <0x01c0f000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC0>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mmc1: mmc@1c10000 {
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+ compatible = "allwinner,sun50i-a64-mmc";
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+ reg = <0x01c10000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC1>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mmc2: mmc@1c11000 {
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+ compatible = "allwinner,sun50i-a64-emmc";
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+ reg = <0x01c11000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC2>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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usb_otg: usb@01c19000 {
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compatible = "allwinner,sun8i-a33-musb";
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reg = <0x01c19000 0x0400>;
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