4fd9028f44
These patches are written by Broadcom and will be in mainline Linux kernel soon. I had some problems to get them backported to kernel 4.1, so currently they are only available for 4.3. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 47253
120 lines
4.1 KiB
Diff
120 lines
4.1 KiB
Diff
From 7c70cb333deb6e2f88da9c94ddd6b3b00c97b93a Mon Sep 17 00:00:00 2001
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From: Jon Mason <jonmason@broadcom.com>
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Date: Thu, 15 Oct 2015 15:48:26 -0400
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Subject: [PATCH 45/50] clk: iproc: Add PWRCTRL support
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Some iProc SoC clocks use a different way to control clock power, via
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the PWRDWN bit in the PLL control register. Since the PLL control
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register is used to access the PWRDWN bit, there is no need for the
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pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL,
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has been added to identify this usage. We can use the AON interface to
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write the values to enable/disable PWRDOWN.
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Signed-off-by: Jon Mason <jonmason@broadcom.com>
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---
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drivers/clk/bcm/clk-iproc-pll.c | 55 ++++++++++++++++++++++++++++-------------
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drivers/clk/bcm/clk-iproc.h | 6 +++++
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2 files changed, 44 insertions(+), 17 deletions(-)
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--- a/drivers/clk/bcm/clk-iproc-pll.c
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+++ b/drivers/clk/bcm/clk-iproc-pll.c
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@@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_p
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writel(val, pll->asiu_base + ctrl->asiu.offset);
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}
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- /* latch input value so core power can be shut down */
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- val = readl(pll->pwr_base + ctrl->aon.offset);
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- val |= (1 << ctrl->aon.iso_shift);
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- writel(val, pll->pwr_base + ctrl->aon.offset);
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-
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- /* power down the core */
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- val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
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- writel(val, pll->pwr_base + ctrl->aon.offset);
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+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
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+ val = readl(pll->pll_base + ctrl->aon.offset);
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+ val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
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+ writel(val, pll->pll_base + ctrl->aon.offset);
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+
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+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
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+ readl(pll->pll_base + ctrl->aon.offset);
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+ }
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+
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+ if (pll->pwr_base) {
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+ /* latch input value so core power can be shut down */
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+ val = readl(pll->pwr_base + ctrl->aon.offset);
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+ val |= (1 << ctrl->aon.iso_shift);
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+ writel(val, pll->pwr_base + ctrl->aon.offset);
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+
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+ /* power down the core */
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+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
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+ writel(val, pll->pwr_base + ctrl->aon.offset);
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+ }
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}
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static int __pll_enable(struct iproc_pll *pll)
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@@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll
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const struct iproc_pll_ctrl *ctrl = pll->ctrl;
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u32 val;
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- /* power up the PLL and make sure it's not latched */
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- val = readl(pll->pwr_base + ctrl->aon.offset);
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- val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
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- val &= ~(1 << ctrl->aon.iso_shift);
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- writel(val, pll->pwr_base + ctrl->aon.offset);
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+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
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+ val = readl(pll->pll_base + ctrl->aon.offset);
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+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
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+ writel(val, pll->pll_base + ctrl->aon.offset);
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+
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+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
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+ readl(pll->pll_base + ctrl->aon.offset);
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+ }
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+
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+ if (pll->pwr_base) {
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+ /* power up the PLL and make sure it's not latched */
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+ val = readl(pll->pwr_base + ctrl->aon.offset);
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+ val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
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+ val &= ~(1 << ctrl->aon.iso_shift);
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+ writel(val, pll->pwr_base + ctrl->aon.offset);
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+ }
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/* certain PLLs also need to be ungated from the ASIU top level */
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if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
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@@ -607,9 +629,8 @@ void __init iproc_pll_clk_setup(struct d
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if (WARN_ON(!pll->pll_base))
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goto err_pll_iomap;
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+ /* Some SoCs do not require the pwr_base, thus failing is not fatal */
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pll->pwr_base = of_iomap(node, 1);
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- if (WARN_ON(!pll->pwr_base))
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- goto err_pwr_iomap;
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/* some PLLs require gating control at the top ASIU level */
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if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) {
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@@ -692,9 +713,9 @@ err_pll_register:
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iounmap(pll->asiu_base);
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err_asiu_iomap:
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- iounmap(pll->pwr_base);
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+ if (pll->pwr_base)
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+ iounmap(pll->pwr_base);
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-err_pwr_iomap:
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iounmap(pll->pll_base);
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err_pll_iomap:
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--- a/drivers/clk/bcm/clk-iproc.h
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+++ b/drivers/clk/bcm/clk-iproc.h
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@@ -49,6 +49,12 @@
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#define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
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/*
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+ * Some PLLs use a different way to control clock power, via the PWRDWN bit in
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+ * the PLL control register
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+ */
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+#define IPROC_CLK_EMBED_PWRCTRL BIT(5)
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+
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+/*
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* Parameters for VCO frequency configuration
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*
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* VCO frequency =
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