c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
121 lines
3.6 KiB
Diff
121 lines
3.6 KiB
Diff
From 610b32220391c9d271290bdf8f2b8fe1cf8da9a0 Mon Sep 17 00:00:00 2001
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From: Bjorn Helgaas <bhelgaas@google.com>
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Date: Tue, 5 Jan 2016 15:48:11 -0600
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Subject: [PATCH 52/70] PCI: designware: Simplify control flow
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Return values immediately when possible to simplify the control flow.
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No functional change intended. Folded in unused variable removal as
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pointed out by Fabio Estevam <fabio.estevam@nxp.com>, Arnd Bergmann
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<arnd@arndb.de>, and Thierry Reding <thierry.reding@gmail.com>.
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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---
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drivers/pci/host/pcie-designware.c | 54 ++++++++++++------------------------
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1 file changed, 18 insertions(+), 36 deletions(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -128,27 +128,19 @@ static inline void dw_pcie_writel_rc(str
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static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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- int ret;
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-
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if (pp->ops->rd_own_conf)
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- ret = pp->ops->rd_own_conf(pp, where, size, val);
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- else
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- ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
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+ return pp->ops->rd_own_conf(pp, where, size, val);
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- return ret;
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+ return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
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}
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static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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- int ret;
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-
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if (pp->ops->wr_own_conf)
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- ret = pp->ops->wr_own_conf(pp, where, size, val);
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- else
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- ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
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+ return pp->ops->wr_own_conf(pp, where, size, val);
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- return ret;
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+ return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
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}
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static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
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@@ -392,8 +384,8 @@ int dw_pcie_link_up(struct pcie_port *pp
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{
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if (pp->ops->link_up)
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return pp->ops->link_up(pp);
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- else
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- return 0;
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+
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+ return 0;
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}
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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@@ -666,46 +658,36 @@ static int dw_pcie_rd_conf(struct pci_bu
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int size, u32 *val)
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{
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struct pcie_port *pp = bus->sysdata;
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- int ret;
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if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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- if (bus->number != pp->root_bus_nr)
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- if (pp->ops->rd_other_conf)
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- ret = pp->ops->rd_other_conf(pp, bus, devfn,
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- where, size, val);
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- else
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- ret = dw_pcie_rd_other_conf(pp, bus, devfn,
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- where, size, val);
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- else
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- ret = dw_pcie_rd_own_conf(pp, where, size, val);
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+ if (bus->number == pp->root_bus_nr)
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+ return dw_pcie_rd_own_conf(pp, where, size, val);
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- return ret;
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+ if (pp->ops->rd_other_conf)
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+ return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
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+
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+ return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
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}
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static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pcie_port *pp = bus->sysdata;
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- int ret;
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if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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- if (bus->number != pp->root_bus_nr)
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- if (pp->ops->wr_other_conf)
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- ret = pp->ops->wr_other_conf(pp, bus, devfn,
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- where, size, val);
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- else
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- ret = dw_pcie_wr_other_conf(pp, bus, devfn,
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- where, size, val);
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- else
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- ret = dw_pcie_wr_own_conf(pp, where, size, val);
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+ if (bus->number == pp->root_bus_nr)
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+ return dw_pcie_wr_own_conf(pp, where, size, val);
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- return ret;
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+ if (pp->ops->wr_other_conf)
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+ return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
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+
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+ return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
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}
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static struct pci_ops dw_pcie_ops = {
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