491 lines
15 KiB
Diff
491 lines
15 KiB
Diff
--- a/drivers/ssb/Kconfig
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+++ b/drivers/ssb/Kconfig
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@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
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If unsure, say N
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+config SSB_SFLASH
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+ bool "SSB serial flash support"
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+ depends on SSB_DRIVER_MIPS && BROKEN
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+ default y
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+
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# Assumption: We are on embedded, if we compile the MIPS core.
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config SSB_EMBEDDED
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bool
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--- a/drivers/ssb/Makefile
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+++ b/drivers/ssb/Makefile
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@@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
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# built-in drivers
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ssb-y += driver_chipcommon.o
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ssb-y += driver_chipcommon_pmu.o
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+ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
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ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
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ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
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ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
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--- /dev/null
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+++ b/drivers/ssb/driver_chipcommon_sflash.c
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@@ -0,0 +1,140 @@
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+/*
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+ * Sonics Silicon Backplane
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+ * ChipCommon serial flash interface
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <linux/ssb/ssb.h>
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+
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+#include "ssb_private.h"
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+
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+struct ssb_sflash_tbl_e {
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+ char *name;
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+ u32 id;
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+ u32 blocksize;
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+ u16 numblocks;
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+};
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+
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+static struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
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+ { "M25P20", 0x11, 0x10000, 4, },
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+ { "M25P40", 0x12, 0x10000, 8, },
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+
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+ { "M25P16", 0x14, 0x10000, 32, },
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+ { "M25P32", 0x15, 0x10000, 64, },
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+ { "M25P64", 0x16, 0x10000, 128, },
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+ { "M25FL128", 0x17, 0x10000, 256, },
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+ { 0 },
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+};
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+
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+static struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
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+ { "SST25WF512", 1, 0x1000, 16, },
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+ { "SST25VF512", 0x48, 0x1000, 16, },
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+ { "SST25WF010", 2, 0x1000, 32, },
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+ { "SST25VF010", 0x49, 0x1000, 32, },
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+ { "SST25WF020", 3, 0x1000, 64, },
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+ { "SST25VF020", 0x43, 0x1000, 64, },
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+ { "SST25WF040", 4, 0x1000, 128, },
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+ { "SST25VF040", 0x44, 0x1000, 128, },
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+ { "SST25VF040B", 0x8d, 0x1000, 128, },
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+ { "SST25WF080", 5, 0x1000, 256, },
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+ { "SST25VF080B", 0x8e, 0x1000, 256, },
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+ { "SST25VF016", 0x41, 0x1000, 512, },
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+ { "SST25VF032", 0x4a, 0x1000, 1024, },
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+ { "SST25VF064", 0x4b, 0x1000, 2048, },
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+ { 0 },
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+};
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+
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+static struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
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+ { "AT45DB011", 0xc, 256, 512, },
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+ { "AT45DB021", 0x14, 256, 1024, },
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+ { "AT45DB041", 0x1c, 256, 2048, },
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+ { "AT45DB081", 0x24, 256, 4096, },
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+ { "AT45DB161", 0x2c, 512, 4096, },
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+ { "AT45DB321", 0x34, 512, 8192, },
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+ { "AT45DB642", 0x3c, 1024, 8192, },
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+ { 0 },
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+};
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+
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+static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
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+{
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+ int i;
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+ chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
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+ SSB_CHIPCO_FLASHCTL_START | opcode);
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+ for (i = 0; i < 1000; i++) {
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+ if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
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+ SSB_CHIPCO_FLASHCTL_BUSY))
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+ return;
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+ cpu_relax();
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+ }
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+ pr_err("SFLASH control command failed (timeout)!\n");
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+}
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+
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+/* Initialize serial flash access */
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+int ssb_sflash_init(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_sflash_tbl_e *e;
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+ u32 id, id2;
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+
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+ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
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+
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+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
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+ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
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+
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+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
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+ id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
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+
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+ switch (id) {
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+ case 0xbf:
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+ for (e = ssb_sflash_sst_tbl; e->name; e++) {
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+ if (e->id == id2)
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+ break;
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+ }
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+ break;
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+ case 0x13:
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+ return -ENOTSUPP;
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+ default:
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+ for (e = ssb_sflash_st_tbl; e->name; e++) {
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+ if (e->id == id)
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+ break;
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+ }
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+ break;
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+ }
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+ if (!e->name) {
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+ pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
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+ id, id2);
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+ return -ENOTSUPP;
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+ }
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+
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+ break;
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
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+ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
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+
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+ for (e = ssb_sflash_at_tbl; e->name; e++) {
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+ if (e->id == id)
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+ break;
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+ }
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+ if (!e->name) {
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+ pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
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+ id);
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+ return -ENOTSUPP;
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+ }
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+
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+ break;
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+ default:
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+ pr_err("Unsupported flash type\n");
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+ return -ENOTSUPP;
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+ }
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+
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+ pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
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+ e->name, e->blocksize, e->numblocks);
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+
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+ pr_err("Serial flash support is not implemented yet!\n");
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+
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+ return -ENOTSUPP;
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+}
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--- a/drivers/ssb/driver_gpio.c
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+++ b/drivers/ssb/driver_gpio.c
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@@ -74,6 +74,16 @@ static void ssb_gpio_chipco_free(struct
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ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
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}
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+static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+
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+ if (bus->bustype == SSB_BUSTYPE_SSB)
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+ return ssb_mips_irq(bus->chipco.dev) + 2;
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+ else
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+ return -EINVAL;
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+}
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+
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static int ssb_gpio_chipco_init(struct ssb_bus *bus)
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{
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struct gpio_chip *chip = &bus->gpio;
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@@ -86,6 +96,7 @@ static int ssb_gpio_chipco_init(struct s
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chip->set = ssb_gpio_chipco_set_value;
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chip->direction_input = ssb_gpio_chipco_direction_input;
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chip->direction_output = ssb_gpio_chipco_direction_output;
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+ chip->to_irq = ssb_gpio_chipco_to_irq;
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chip->ngpio = 16;
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/* There is just one SoC in one device and its GPIO addresses should be
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* deterministic to address them more easily. The other buses could get
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@@ -134,6 +145,16 @@ static int ssb_gpio_extif_direction_outp
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return 0;
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}
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+static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+
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+ if (bus->bustype == SSB_BUSTYPE_SSB)
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+ return ssb_mips_irq(bus->extif.dev) + 2;
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+ else
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+ return -EINVAL;
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+}
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+
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static int ssb_gpio_extif_init(struct ssb_bus *bus)
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{
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struct gpio_chip *chip = &bus->gpio;
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@@ -144,6 +165,7 @@ static int ssb_gpio_extif_init(struct ss
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chip->set = ssb_gpio_extif_set_value;
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chip->direction_input = ssb_gpio_extif_direction_input;
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chip->direction_output = ssb_gpio_extif_direction_output;
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+ chip->to_irq = ssb_gpio_extif_to_irq;
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chip->ngpio = 5;
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/* There is just one SoC in one device and its GPIO addresses should be
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* deterministic to address them more easily. The other buses could get
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -10,6 +10,7 @@
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#include <linux/ssb/ssb.h>
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+#include <linux/mtd/physmap.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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@@ -17,6 +18,25 @@
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#include "ssb_private.h"
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+static const char *part_probes[] = { "bcm47xxpart", NULL };
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+
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+static struct physmap_flash_data ssb_pflash_data = {
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+ .part_probe_types = part_probes,
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+};
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+
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+static struct resource ssb_pflash_resource = {
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+ .name = "ssb_pflash",
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+struct platform_device ssb_pflash_dev = {
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+ .name = "physmap-flash",
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+ .dev = {
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+ .platform_data = &ssb_pflash_data,
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+ },
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+ .resource = &ssb_pflash_resource,
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+ .num_resources = 1,
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+};
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static inline u32 mips_read32(struct ssb_mipscore *mcore,
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u16 offset)
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@@ -189,34 +209,43 @@ static void ssb_mips_serial_init(struct
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static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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+ struct ssb_pflash *pflash = &mcore->pflash;
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/* When there is no chipcommon on the bus there is 4MB flash */
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if (!ssb_chipco_available(&bus->chipco)) {
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- mcore->pflash.present = true;
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- mcore->pflash.buswidth = 2;
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- mcore->pflash.window = SSB_FLASH1;
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- mcore->pflash.window_size = SSB_FLASH1_SZ;
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- return;
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+ pflash->present = true;
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+ pflash->buswidth = 2;
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+ pflash->window = SSB_FLASH1;
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+ pflash->window_size = SSB_FLASH1_SZ;
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+ goto ssb_pflash;
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}
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/* There is ChipCommon, so use it to read info about flash */
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switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
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case SSB_CHIPCO_FLASHT_STSER:
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case SSB_CHIPCO_FLASHT_ATSER:
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- pr_err("Serial flash not supported\n");
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+ pr_debug("Found serial flash\n");
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+ ssb_sflash_init(&bus->chipco);
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break;
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case SSB_CHIPCO_FLASHT_PARA:
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pr_debug("Found parallel flash\n");
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- mcore->pflash.present = true;
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- mcore->pflash.window = SSB_FLASH2;
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- mcore->pflash.window_size = SSB_FLASH2_SZ;
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+ pflash->present = true;
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+ pflash->window = SSB_FLASH2;
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+ pflash->window_size = SSB_FLASH2_SZ;
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if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
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& SSB_CHIPCO_CFG_DS16) == 0)
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- mcore->pflash.buswidth = 1;
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+ pflash->buswidth = 1;
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else
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- mcore->pflash.buswidth = 2;
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+ pflash->buswidth = 2;
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break;
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}
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+
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+ssb_pflash:
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+ if (pflash->present) {
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+ ssb_pflash_data.width = pflash->buswidth;
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+ ssb_pflash_resource.start = pflash->window;
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+ ssb_pflash_resource.end = pflash->window + pflash->window_size;
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+ }
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}
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u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -549,6 +549,14 @@ static int ssb_devices_register(struct s
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dev_idx++;
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}
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+#ifdef CONFIG_SSB_DRIVER_MIPS
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+ if (bus->mipscore.pflash.present) {
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+ err = platform_device_register(&ssb_pflash_dev);
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+ if (err)
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+ pr_err("Error registering parallel flash\n");
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+ }
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+#endif
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+
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return 0;
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error:
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/* Unwind the already registered devices. */
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--- a/drivers/ssb/ssb_private.h
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+++ b/drivers/ssb/ssb_private.h
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@@ -217,6 +217,21 @@ extern u32 ssb_chipco_watchdog_timer_set
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u32 ticks);
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extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
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+/* driver_chipcommon_sflash.c */
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+#ifdef CONFIG_SSB_SFLASH
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+int ssb_sflash_init(struct ssb_chipcommon *cc);
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+#else
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+static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
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+{
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+ pr_err("Serial flash not supported\n");
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+ return 0;
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+}
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+#endif /* CONFIG_SSB_SFLASH */
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+
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+#ifdef CONFIG_SSB_DRIVER_MIPS
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+extern struct platform_device ssb_pflash_dev;
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+#endif
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+
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#ifdef CONFIG_SSB_DRIVER_EXTIF
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extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
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extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
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--- a/include/linux/ssb/ssb_driver_mips.h
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+++ b/include/linux/ssb/ssb_driver_mips.h
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@@ -45,6 +45,11 @@ void ssb_mipscore_init(struct ssb_mipsco
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{
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}
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+static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
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+{
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+ return 0;
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+}
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+
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#endif /* CONFIG_SSB_DRIVER_MIPS */
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#endif /* LINUX_SSB_MIPSCORE_H_ */
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--- a/drivers/net/wireless/b43/phy_n.c
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+++ b/drivers/net/wireless/b43/phy_n.c
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@@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru
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#endif
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#ifdef CONFIG_B43_SSB
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case B43_BUS_SSB:
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- /* FIXME */
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+ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
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+ avoid);
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break;
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#endif
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}
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -675,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
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return 0;
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}
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}
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+
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+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
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+{
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+ u32 pmu_ctl = 0;
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+
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+ switch (cc->dev->bus->chip_id) {
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+ case 0x4322:
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
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+ if (spuravoid == 1)
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
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+ else
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
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+ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
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+ break;
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+ case 43222:
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+ /* TODO: BCM43222 requires updating PLLs too */
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+ return;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
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+ cc->dev->bus->chip_id);
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+ return;
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+ }
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+
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+ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
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+}
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+EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
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return (s8)gain;
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}
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+static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
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+{
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+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
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+ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
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+ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
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+ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
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+ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
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+ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
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+ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
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+ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
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+ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
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+ SSB_SPROM2_MAXP_A_LO_SHIFT);
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+}
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+
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static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
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SSB_SPROM1_ITSSI_A_SHIFT);
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SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
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SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
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- if (out->revision >= 2)
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- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+
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SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
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SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
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|
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@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
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out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
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SSB_SPROM1_AGAIN_A,
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SSB_SPROM1_AGAIN_A_SHIFT);
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+ if (out->revision >= 2)
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+ sprom_extract_r23(out, in);
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}
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|
|
|
/* Revs 4 5 and 8 have partially shared layout */
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
|
@@ -219,6 +219,7 @@
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|
#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
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|
#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
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#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
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|
+#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
|
|
#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
|
|
#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
|
|
#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
|
|
@@ -667,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
|
|
void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
|
|
enum ssb_pmu_ldo_volt_id id, u32 voltage);
|
|
void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
|
|
+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
|
|
|
|
#endif /* LINUX_SSB_CHIPCO_H_ */
|
|
--- a/include/linux/ssb/ssb_regs.h
|
|
+++ b/include/linux/ssb/ssb_regs.h
|
|
@@ -289,11 +289,11 @@
|
|
#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
|
|
#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
|
|
#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
|
|
-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
|
|
-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
|
|
-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
|
|
-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
|
|
-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
|
|
+#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
|
|
+#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
|
|
+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
|
|
+#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
|
|
+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
|
|
#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
|
|
#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
|
|
#define SSB_SPROM4_AGAIN0_SHIFT 0
|