50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
From 79d0293e8f35e87b1f068fc0b7963a86ba56800e Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Thu, 28 Dec 2017 15:46:42 +0800
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Subject: [PATCH 211/224] arm64: dts: mt7622: add power domain controller
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device nodes
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add power domain controller nodes
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Cc: Matthias Brugger <matthias.bgg@gmail.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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index 73e5d628a8c8..81207e652d59 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -9,6 +9,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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+#include <dt-bindings/power/mt7622-power.h>
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#include <dt-bindings/reset/mt7622-reset.h>
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/ {
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@@ -109,6 +110,20 @@
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#reset-cells = <1>;
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};
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+ scpsys: scpsys@10006000 {
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+ compatible = "mediatek,mt7622-scpsys",
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+ "syscon";
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+ #power-domain-cells = <1>;
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+ reg = <0 0x10006000 0 0x1000>;
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+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
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+ infracfg = <&infracfg>;
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+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
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+ clock-names = "hif_sel";
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+ };
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+
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,mt7622-sysirq",
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"mediatek,mt6577-sysirq";
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--
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2.11.0
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