60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
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index dfb0a3e..7a6a3cc 100644
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--- a/arch/arm/cpu/armv7/sunxi/Makefile
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+++ b/arch/arm/cpu/armv7/sunxi/Makefile
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@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
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endif
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obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
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obj-$(CONFIG_MACH_SUN6I) += tzpc.o
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+obj-$(CONFIG_MACH_SUN8I) += tzpc.o
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obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
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obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
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diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
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index 5c9c69b..6c8a0fd 100644
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--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
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+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
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@@ -13,6 +13,15 @@ void tzpc_init(void)
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{
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struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
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+#ifdef CONFIG_MACH_SUN6I
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/* Enable non-secure access to the RTC */
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- writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
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+ writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
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+#endif
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+
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+#ifdef CONFIG_MACH_SUN8I_H3
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+ /* Enable non-secure access to all peripherals */
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+ writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
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+ writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
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+ writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
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+#endif
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}
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diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
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index ba4d43b..95c55cd 100644
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--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
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+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
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@@ -13,10 +13,21 @@ struct sunxi_tzpc {
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u32 decport0_status; /* 0x04 Status of decode protection port 0 */
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u32 decport0_set; /* 0x08 Set decode protection port 0 */
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u32 decport0_clear; /* 0x0c Clear decode protection port 0 */
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+ /* For A80 and later SoCs */
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+ u32 decport1_status; /* 0x10 Status of decode protection port 1 */
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+ u32 decport1_set; /* 0x14 Set decode protection port 1 */
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+ u32 decport1_clear; /* 0x18 Clear decode protection port 1 */
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+ u32 decport2_status; /* 0x1c Status of decode protection port 2 */
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+ u32 decport2_set; /* 0x20 Set decode protection port 2 */
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+ u32 decport2_clear; /* 0x24 Clear decode protection port 2 */
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};
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#endif
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-#define SUNXI_TZPC_DECPORT0_RTC (1 << 1)
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+#define SUN6I_TZPC_DECPORT0_RTC (1 << 1)
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+
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+#define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe
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+#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff
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+#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f
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void tzpc_init(void);
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