cae808946a
Add patches and config for 4.14, refreshed from 4.9. Signed-off-by: Matti Laakso <matti.laakso@outlook.com>
49 lines
2 KiB
Diff
49 lines
2 KiB
Diff
From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001
|
|
From: Govindraj Raja <Govindraj.Raja@imgtec.com>
|
|
Date: Fri, 8 Jan 2016 16:36:07 +0000
|
|
Subject: clk: pistachio: Fix wrong SDHost card speed
|
|
|
|
The SDHost currently clocks the card 4x slower than it
|
|
should do, because there is fixed divide by 4 in the
|
|
sdhost wrapper that is not present in the clock tree.
|
|
To model this add a fixed divide by 4 clock node in
|
|
the SDHost clock path.
|
|
|
|
This will ensure the right clock frequency is selected when
|
|
the mmc driver tries to configure frequency on card insert.
|
|
|
|
Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
|
|
---
|
|
drivers/clk/pistachio/clk-pistachio.c | 3 ++-
|
|
include/dt-bindings/clock/pistachio-clk.h | 1 +
|
|
2 files changed, 3 insertions(+), 1 deletion(-)
|
|
|
|
--- a/drivers/clk/pistachio/clk-pistachio.c
|
|
+++ b/drivers/clk/pistachio/clk-pistachio.c
|
|
@@ -44,7 +44,7 @@ static struct pistachio_gate pistachio_g
|
|
GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
|
|
0x104, 22),
|
|
GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
|
|
- GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
|
|
+ GATE(CLK_SD_HOST, "sd_host", "sd_host_div4", 0x104, 24),
|
|
GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
|
|
GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
|
|
GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
|
|
@@ -54,6 +54,7 @@ static struct pistachio_gate pistachio_g
|
|
static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
|
|
FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
|
|
FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
|
|
+ FIXED_FACTOR(CLK_SDHOST_DIV4, "sd_host_div4", "sd_host_div", 4),
|
|
};
|
|
|
|
static struct pistachio_div pistachio_divs[] __initdata = {
|
|
--- a/include/dt-bindings/clock/pistachio-clk.h
|
|
+++ b/include/dt-bindings/clock/pistachio-clk.h
|
|
@@ -21,6 +21,7 @@
|
|
/* Fixed-factor clocks */
|
|
#define CLK_WIFI_DIV4 16
|
|
#define CLK_WIFI_DIV8 17
|
|
+#define CLK_SDHOST_DIV4 18
|
|
|
|
/* Gate clocks */
|
|
#define CLK_MIPS 32
|