c9c68c7177
An external reset patch for AR955x accidentally led to external reset being issued twice on AR913x, once before the RTC reset and once after. This may be causing some stability issues. Signed-off-by: Felix Fietkau <nbd@nbd.name>
79 lines
2 KiB
Diff
79 lines
2 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -246,6 +246,19 @@ void ath9k_hw_get_channel_centers(struct
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centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}
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+static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah)
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+{
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+ /* On AR9330 and AR9340 devices, some PHY registers must be
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+ * tuned to gain better stability/performance. These registers
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+ * might be changed while doing wlan reset so the registers must
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+ * be reprogrammed after each reset.
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+ */
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+ REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20));
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+ REG_RMW(ah, AR_PHY_USB_CTRL2,
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+ (1 << 21) | (0xf << 22),
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+ (1 << 21) | (0x3 << 22));
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+}
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+
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/******************/
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/* Chip Revisions */
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/******************/
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@@ -1414,6 +1427,9 @@ static bool ath9k_hw_set_reset(struct at
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udelay(50);
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}
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+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
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+ ath9k_hw_disable_pll_lock_detect(ah);
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+
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return true;
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}
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@@ -1513,6 +1529,9 @@ static bool ath9k_hw_chip_reset(struct a
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ar9003_hw_internal_regulator_apply(ah);
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ath9k_hw_init_pll(ah, chan);
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+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
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+ ath9k_hw_disable_pll_lock_detect(ah);
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+
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return true;
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}
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@@ -1816,8 +1835,14 @@ static int ath9k_hw_do_fastcc(struct ath
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if (AR_SREV_9271(ah))
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ar9002_hw_load_ani_reg(ah, chan);
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+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
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+ ath9k_hw_disable_pll_lock_detect(ah);
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+
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return 0;
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fail:
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+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
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+ ath9k_hw_disable_pll_lock_detect(ah);
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+
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return -EINVAL;
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}
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@@ -2071,6 +2096,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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ath9k_hw_set_radar_params(ah);
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}
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+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
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+ ath9k_hw_disable_pll_lock_detect(ah);
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+
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return 0;
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}
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EXPORT_SYMBOL(ath9k_hw_reset);
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--- a/drivers/net/wireless/ath/ath9k/phy.h
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+++ b/drivers/net/wireless/ath/ath9k/phy.h
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@@ -48,6 +48,9 @@
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#define AR_PHY_PLL_CONTROL 0x16180
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#define AR_PHY_PLL_MODE 0x16184
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+#define AR_PHY_USB_CTRL1 0x16c84
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+#define AR_PHY_USB_CTRL2 0x16c88
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+
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enum ath9k_ant_div_comb_lna_conf {
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ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
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ATH_ANT_DIV_COMB_LNA2,
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