99 lines
3.4 KiB
Diff
99 lines
3.4 KiB
Diff
From 14ef339843c24bf449d0f6d8bc176368c331c2c8 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 7 Dec 2015 17:29:00 +0100
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Subject: [PATCH 21/53] arch: mips: ralink: add mt7688 detection
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
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arch/mips/include/asm/mach-ralink/ralink_regs.h | 1 +
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arch/mips/ralink/mt7620.c | 21 ++++++++++++++++-----
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3 files changed, 18 insertions(+), 5 deletions(-)
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diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
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index 0ef882b..455d406 100644
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--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -17,6 +17,7 @@
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#define SYSC_REG_CHIP_NAME0 0x00
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#define SYSC_REG_CHIP_NAME1 0x04
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+#define SYSC_REG_EFUSE_CFG 0x08
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
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index 8fcbd0f..69fbcec 100644
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--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
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+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
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@@ -24,6 +24,7 @@ enum ralink_soc_type {
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MT762X_SOC_MT7620N,
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MT762X_SOC_MT7621AT,
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MT762X_SOC_MT7628AN,
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+ MT762X_SOC_MT7688,
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};
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extern enum ralink_soc_type ralink_soc;
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diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
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index 41b4a3e..6975ed8 100644
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -46,6 +46,9 @@ enum mt762x_soc_type mt762x_soc;
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#define CLKCFG_FFRAC_MASK 0x001f
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#define CLKCFG_FFRAC_USB_VAL 0x0003
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+/* EFUSE bits */
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+#define EFUSE_MT7688 0x100000
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+
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/* does the board have sdram or ddram */
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static int dram_type;
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@@ -407,7 +410,7 @@ void __init ralink_clk_init(void)
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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- if (mt762x_soc == MT762X_SOC_MT7628AN) {
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+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
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if (xtal_rate == MHZ(40))
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cpu_rate = MHZ(580);
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else
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@@ -451,7 +454,8 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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- if (IS_ENABLED(CONFIG_USB)) {
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+ if (IS_ENABLED(CONFIG_USB) &&
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+ (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be too low for
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* USB to function properly
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@@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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soc_info->compatible = "ralink,mt7620n-soc";
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}
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} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
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- mt762x_soc = MT762X_SOC_MT7628AN;
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- name = "MT7628AN";
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+ u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
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+
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+ if (efuse & EFUSE_MT7688) {
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+ mt762x_soc = MT762X_SOC_MT7688;
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+ name = "MT7688";
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+ } else {
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+ mt762x_soc = MT762X_SOC_MT7628AN;
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+ name = "MT7628AN";
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+ }
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soc_info->compatible = "ralink,mt7628an-soc";
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} else {
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panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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@@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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pr_info("Digital PMU set to %s control\n",
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(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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- if (mt762x_soc == MT762X_SOC_MT7628AN)
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+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
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rt2880_pinmux_data = mt7628an_pinmux_data;
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else
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rt2880_pinmux_data = mt7620a_pinmux_data;
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--
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1.7.10.4
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