64b53247c4
Refresh patches. Remove upstreamed patch: generic/pending/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch Update patches that no longer applies: generic/hack/901-debloat_sock_diag.patch Compile-tested on: x86/64. Runtime-tested on: x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
119 lines
3 KiB
Diff
119 lines
3 KiB
Diff
From 3e23988f5c9c5d54732eda1e8017409ef223048b Mon Sep 17 00:00:00 2001
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From: Chunfeng Yun <chunfeng.yun@mediatek.com>
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Date: Fri, 12 Jan 2018 12:28:31 +0800
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Subject: [PATCH 221/224] arm64: dts: mt7622: add usb device nodes
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add xhci node and usb3 phy nodes
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Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Tested-by: Jumin Li <jumin.li@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 28 +++++++++++++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 51 ++++++++++++++++++++++++++++
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2 files changed, 79 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -52,6 +52,24 @@
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memory {
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reg = <0 0x40000000 0 0x3F000000>;
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};
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_5v: regulator-5v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-5V";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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};
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&pcie {
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@@ -343,6 +361,16 @@
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status = "okay";
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};
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+&ssusb {
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+ vusb33-supply = <®_3p3v>;
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+ vbus-supply = <®_5v>;
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+ status = "okay";
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+};
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+
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+&u3phy {
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+ status = "okay";
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+};
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+
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -535,6 +535,57 @@
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#reset-cells = <1>;
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};
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+ ssusb: usb@1a0c0000 {
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+ compatible = "mediatek,mt7622-xhci",
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+ "mediatek,mtk-xhci";
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+ reg = <0 0x1a0c0000 0 0x01000>,
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+ <0 0x1a0c4700 0 0x0100>;
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+ reg-names = "mac", "ippc";
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+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
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+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
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+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
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+ <&ssusbsys CLK_SSUSB_REF_EN>,
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+ <&ssusbsys CLK_SSUSB_MCU_EN>,
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+ <&ssusbsys CLK_SSUSB_DMA_EN>;
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+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
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+ phys = <&u2port0 PHY_TYPE_USB2>,
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+ <&u3port0 PHY_TYPE_USB3>,
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+ <&u2port1 PHY_TYPE_USB2>;
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+
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+ status = "disabled";
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+ };
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+
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+ u3phy: usb-phy@1a0c4000 {
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+ compatible = "mediatek,mt7622-u3phy",
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+ "mediatek,generic-tphy-v1";
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+ reg = <0 0x1a0c4000 0 0x700>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ u2port0: usb-phy@1a0c4800 {
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+ reg = <0 0x1a0c4800 0 0x0100>;
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+ #phy-cells = <1>;
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+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
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+ clock-names = "ref";
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+ };
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+
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+ u3port0: usb-phy@1a0c4900 {
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+ reg = <0 0x1a0c4900 0 0x0700>;
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+ #phy-cells = <1>;
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+ clocks = <&clk25m>;
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+ clock-names = "ref";
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+ };
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+
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+ u2port1: usb-phy@1a0c5000 {
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+ reg = <0 0x1a0c5000 0 0x0100>;
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+ #phy-cells = <1>;
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+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
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+ clock-names = "ref";
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+ };
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+ };
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+
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pciesys: pciesys@1a100800 {
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compatible = "mediatek,mt7622-pciesys",
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"syscon";
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