bb39b8d99a
Update our copies of the brcm2708 patches to the latest rpi-3.10-y rebased against linux-3.10.y stable (3.10.32). This should hopefully make it easier for us in the future to leverage the raspberry/rpi-* branches. Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 39770
64 lines
2.3 KiB
Diff
64 lines
2.3 KiB
Diff
From cb902630ae7ef709c8f40ca3f506cf5052077701 Mon Sep 17 00:00:00 2001
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From: P33M <P33M@github.com>
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Date: Sat, 13 Jul 2013 20:41:26 +0100
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Subject: [PATCH 078/174] dwc_otg: mask correct interrupts after transaction
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error recovery
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The dwc_otg driver will unmask certain interrupts on a transaction
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that previously halted in the error state in order to reset the
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QTD error count. The various fine-grained interrupt handlers do not
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consider that other interrupts besides themselves were unmasked.
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By disabling the two other interrupts only ever enabled in DMA mode
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for this purpose, we can avoid unnecessary function calls in the
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IRQ handler. This will also prevent an unneccesary FIQ interrupt
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from being generated if the FIQ is enabled.
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---
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drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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@@ -1851,7 +1851,11 @@ static int32_t handle_hc_nak_intr(dwc_ot
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* transfers in DMA mode for the sole purpose of
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* resetting the error count after a transaction error
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* occurs. The core will continue transferring data.
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+ * Disable other interrupts unmasked for the same
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+ * reason.
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*/
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+ disable_hc_int(hc_regs, datatglerr);
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+ disable_hc_int(hc_regs, ack);
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qtd->error_count = 0;
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goto handle_nak_done;
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}
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@@ -1963,6 +1967,15 @@ static int32_t handle_hc_ack_intr(dwc_ot
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halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
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}
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} else {
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+ /*
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+ * An unmasked ACK on a non-split DMA transaction is
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+ * for the sole purpose of resetting error counts. Disable other
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+ * interrupts unmasked for the same reason.
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+ */
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+ if(hcd->core_if->dma_enable) {
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+ disable_hc_int(hc_regs, datatglerr);
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+ disable_hc_int(hc_regs, nak);
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+ }
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qtd->error_count = 0;
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if (hc->qh->ping_state) {
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@@ -2328,6 +2341,14 @@ static int32_t handle_hc_datatglerr_intr
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qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
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halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
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} else if (hc->ep_is_in) {
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+ /* An unmasked data toggle error on a non-split DMA transaction is
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+ * for the sole purpose of resetting error counts. Disable other
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+ * interrupts unmasked for the same reason.
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+ */
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+ if(hcd->core_if->dma_enable) {
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+ disable_hc_int(hc_regs, ack);
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+ disable_hc_int(hc_regs, nak);
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+ }
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qtd->error_count = 0;
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}
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