dc7efaefb5
Hardware Highlights:
This patch adds support for Western Digital MyBook Live Series:
CPU: AMCC PowerPC UNKNOWN (PVR=12c41c83) at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
32 kB I-Cache 32 kB D-Cache, 256 kB L2-Cache, 32 kB OnChip Memory
Board: Apollo-3G - APM82181 Board, 1*SATA
DRAM: 256 MB (2x NT5TU64M16GG-AC)
FLASH: 512 kB (SST 39VF040)
Ethernet: 1xRGMII - 1 Gbit - Broadcom PHY BCM54610
WARNING: The serial port needs a TTL/RS-232 v3.3 level converter!
The MyBook Live Duo additionally features a 1x USB 2.0 host port
and can support a second hard-drive.
This target produces two images for a target.
1. ext4 image
The extracted/raw image can be directly installed on
the internal HDD via "dd if=img.ext4 of=/dev/sdX".
This can either be done in place with the stock MyBook Live
firmware via ssh. Or by removing the HDD and writing the image
with a different PC.
The the compressed images are useful for sysupgrade.
2. recovery.tar image for TFTP and Serial.
extract the recovery.tar to a TFTP server directory.
On the MyBook Live (Duo) serial port - Hit Enter during u-boot and insert:
# setenv serverip 192.168.1.254; setenv ipaddr 192.168.1.1; run net_self
Where 192.168.1.254 is your TFTP server.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
95 lines
3.6 KiB
Diff
95 lines
3.6 KiB
Diff
From: Arnd Bergmann <arnd@arndb.de>
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Subject: [PATCH v4] usb: dwc2: fix regression on big-endian PowerPC/ARM systems
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Date: Fri, 13 May 2016 15:52:27 +0200
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Message-Id: <1463147559-544140-1-git-send-email-arnd@arndb.de>
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A patch that went into Linux-4.4 to fix big-endian mode on a Lantiq
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MIPS system unfortunately broke big-endian operation on PowerPC
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APM82181 as reported by Christian Lamparter, and likely other
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systems.
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It actually introduced multiple issues:
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- it broke big-endian ARM kernels: any machine that was working
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correctly with a little-endian kernel is no longer using byteswaps
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on big-endian kernels, which clearly breaks them.
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- On PowerPC the same thing must be true: if it was working before,
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using big-endian kernels is now broken. Unlike ARM, 32-bit PowerPC
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usually uses big-endian kernels, so they are likely all broken.
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- The barrier for dwc2_writel is on the wrong side of the __raw_writel(),
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so the MMIO no longer synchronizes with DMA operations.
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- On architectures that require specific CPU instructions for MMIO
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access, using the __raw_ variant may turn this into a pointer
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dereference that does not have the same effect as the readl/writel.
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This patch is a simple revert for all architectures other than MIPS,
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in the hope that we can more easily backport it to fix the regression
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on PowerPC and ARM systems without breaking the Lantiq system again.
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We should follow this up with a more elaborate change to add runtime
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detection of endianness, to make sure it also works on all other
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combinations of architectures and implementations of the usb-dwc2
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device. That patch however will be fairly large and not appropriate
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for backports to stable kernels.
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Felipe suggested a different approach, using an endianness switching
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register to always put the device into LE mode, but unfortunately
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the dwc2 hardware does not provide a generic way to do that. Also,
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I see no practical way of addressing the problem more generally by
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patching architecture specific code on MIPS.
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Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Fixes: 95c8bc360944 ("usb: dwc2: Use platform endianness when accessing registers")
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---
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drivers/usb/dwc2/core.h | 27 +++++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
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index 3c58d633ce80..dec0b21fc626 100644
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--- a/drivers/usb/dwc2/core.h
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+++ b/drivers/usb/dwc2/core.h
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@@ -64,6 +64,17 @@
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DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
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dev_name(hsotg->dev), ##__VA_ARGS__)
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+#ifdef CONFIG_MIPS
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+/*
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+ * There are some MIPS machines that can run in either big-endian
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+ * or little-endian mode and that use the dwc2 register without
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+ * a byteswap in both ways.
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+ * Unlike other architectures, MIPS apparently does not require a
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+ * barrier before the __raw_writel() to synchronize with DMA but does
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+ * require the barrier after the __raw_writel() to serialize a set of
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+ * writes. This set of operations was added specifically for MIPS and
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+ * should only be used there.
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+ */
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static inline u32 dwc2_readl(const void __iomem *addr)
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{
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u32 value = __raw_readl(addr);
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@@ -90,6 +101,22 @@ static inline void dwc2_writel(u32 value, void __iomem *addr)
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pr_info("INFO:: wrote %08x to %p\n", value, addr);
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#endif
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}
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+#else
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+/* Normal architectures just use readl/write */
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+static inline u32 dwc2_readl(const void __iomem *addr)
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+{
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+ return readl(addr);
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+}
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+
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+static inline void dwc2_writel(u32 value, void __iomem *addr)
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+{
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+ writel(value, addr);
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+
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+#ifdef DWC2_LOG_WRITES
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+ pr_info("info:: wrote %08x to %p\n", value, addr);
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+#endif
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+}
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+#endif
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/* Maximum number of Endpoints/HostChannels */
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#define MAX_EPS_CHANNELS 16
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--
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2.7.0
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