7e20e4ab96
Refreshed all patches. Removed upstreamed hunks in: - 703-phy-support-layerscape.patch Compile-tested on: ar71xx, layerscape Runtime-tested on: ar71xx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
29 lines
1.4 KiB
Diff
29 lines
1.4 KiB
Diff
From b0fcb4b413028376894feaaaf62bcb09ab1b52f2 Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Thu, 13 Apr 2017 09:23:54 +0200
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Subject: [PATCH] mtd: spi-nor: enable stateless 4b op codes for mx25u25635f
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All required stateless 4-byte op codes are supported by this flash
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chip. The stateless 4-byte support can't be autodetected due to a
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missing 4-byte Address Instruction Table in SFDP.
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Fixes hangs on reboot for SoCs expecting the flash chip in 3byte mode.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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Acked-by: Marek Vasut <marek.vasut@gmail.com>
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -1023,7 +1023,7 @@ static const struct flash_info spi_nor_i
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{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
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{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
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{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
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- { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
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+ { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
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{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
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{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
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{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
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