67 lines
2 KiB
C
67 lines
2 KiB
C
/*
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* Broadcom BCM47xx Performance Counter /proc/cpuinfo support
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#include <asm/mipsregs.h>
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/*
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* BCM4710 performance counter register select values
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* No even-odd control-counter mapping, just counters
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*/
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#define PERF_DCACHE_HIT 0
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#define PERF_DCACHE_MISS 1
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#define PERF_ICACHE_HIT 2
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#define PERF_ICACHE_MISS 3
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#define PERF_ICOUNT 4
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/*
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* Move from Coprocessor 0 Register 25 Select n
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* data <- CPR[0,25,n]
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* GPR[1] <- data
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*/
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#define read_bcm4710_perf_cntr(n) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n\t" \
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".word\t"STR(0x4001c800|(n))"\n\t" \
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"move\t%0,$1\n\t" \
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".set\tat\n\t" \
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".set\treorder" \
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:"=r" (__res)); \
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__res;})
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asmlinkage unsigned int read_perf_cntr(unsigned int counter)
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{
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switch (counter) {
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case PERF_DCACHE_HIT: return read_bcm4710_perf_cntr(PERF_DCACHE_HIT);
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case PERF_DCACHE_MISS: return read_bcm4710_perf_cntr(PERF_DCACHE_MISS);
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case PERF_ICACHE_HIT: return read_bcm4710_perf_cntr(PERF_ICACHE_HIT);
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case PERF_ICACHE_MISS: return read_bcm4710_perf_cntr(PERF_ICACHE_MISS);
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case PERF_ICOUNT: return read_bcm4710_perf_cntr(PERF_ICOUNT);
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}
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return 0;
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}
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asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val)
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{
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}
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asmlinkage unsigned int read_perf_cntl(unsigned int counter)
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{
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return 0;
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}
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asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val)
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{
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}
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