446 lines
10 KiB
C
446 lines
10 KiB
C
/*
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* Atheros AR71xx SoC specific setup
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h> /* for mips_hpt_frequency */
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#include <asm/reboot.h> /* for _machine_{restart,halt} */
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#include <asm/mips_machine.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include "machtype.h"
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#include "devices.h"
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#define AR71XX_SYS_TYPE_LEN 64
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u32 ar71xx_cpu_freq;
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EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
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u32 ar71xx_ahb_freq;
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EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
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u32 ar71xx_ddr_freq;
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EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
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u32 ar71xx_ref_freq;
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EXPORT_SYMBOL_GPL(ar71xx_ref_freq);
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enum ar71xx_soc_type ar71xx_soc;
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EXPORT_SYMBOL_GPL(ar71xx_soc);
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u32 ar71xx_soc_rev;
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EXPORT_SYMBOL_GPL(ar71xx_soc_rev);
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static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
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static void ar71xx_restart(char *command)
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{
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ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
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for (;;)
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if (cpu_wait)
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cpu_wait();
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}
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static void ar71xx_halt(void)
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{
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while (1)
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cpu_wait();
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}
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static void __init ar71xx_detect_mem_size(void)
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{
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unsigned long size;
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for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
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size <<= 1) {
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if (!memcmp(ar71xx_detect_mem_size,
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ar71xx_detect_mem_size + size, 1024))
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break;
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}
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add_memory_region(0, size, BOOT_MEM_RAM);
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}
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static void __init ar71xx_detect_sys_type(void)
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{
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char *chip = "????";
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u32 id;
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u32 major;
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u32 minor;
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u32 rev = 0;
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id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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switch (major) {
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case REV_ID_MAJOR_AR71XX:
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minor = id & AR71XX_REV_ID_MINOR_MASK;
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rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
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rev &= AR71XX_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR71XX_REV_ID_MINOR_AR7130:
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ar71xx_soc = AR71XX_SOC_AR7130;
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chip = "7130";
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break;
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case AR71XX_REV_ID_MINOR_AR7141:
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ar71xx_soc = AR71XX_SOC_AR7141;
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chip = "7141";
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break;
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case AR71XX_REV_ID_MINOR_AR7161:
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ar71xx_soc = AR71XX_SOC_AR7161;
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chip = "7161";
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break;
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}
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break;
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case REV_ID_MAJOR_AR7240:
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ar71xx_soc = AR71XX_SOC_AR7240;
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chip = "7240";
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rev = id & AR724X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR7241:
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ar71xx_soc = AR71XX_SOC_AR7241;
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chip = "7241";
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rev = id & AR724X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR7242:
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ar71xx_soc = AR71XX_SOC_AR7242;
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chip = "7242";
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rev = id & AR724X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR913X:
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minor = id & AR91XX_REV_ID_MINOR_MASK;
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rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
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rev &= AR91XX_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR91XX_REV_ID_MINOR_AR9130:
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ar71xx_soc = AR71XX_SOC_AR9130;
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chip = "9130";
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break;
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case AR91XX_REV_ID_MINOR_AR9132:
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ar71xx_soc = AR71XX_SOC_AR9132;
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chip = "9132";
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break;
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}
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break;
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case REV_ID_MAJOR_AR9330:
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ar71xx_soc = AR71XX_SOC_AR9330;
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chip = "9330";
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rev = id & AR933X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9331:
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ar71xx_soc = AR71XX_SOC_AR9331;
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chip = "9331";
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rev = id & AR933X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9342:
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ar71xx_soc = AR71XX_SOC_AR9342;
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chip = "9342";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9344:
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ar71xx_soc = AR71XX_SOC_AR9344;
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chip = "9344";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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default:
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panic("ar71xx: unknown chip id:0x%08x\n", id);
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}
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ar71xx_soc_rev = rev;
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sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
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pr_info("SoC: %s\n", ar71xx_sys_type);
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}
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static void __init ar934x_detect_sys_frequency(void)
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{
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
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ar71xx_ref_freq = 40 * 1000 * 1000;
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else
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ar71xx_ref_freq = 25 * 1000 * 1000;
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clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
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pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
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out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
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ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
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nint = AR934X_CPU_PLL_CFG_NINT_GET(pll);
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frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
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postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
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ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
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(postdiv + 1);
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out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
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ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
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nint = AR934X_DDR_PLL_CFG_NINT_GET(pll);
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frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
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postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
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ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
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(postdiv + 1);
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postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
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if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
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ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
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} else {
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ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
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}
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}
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static void __init ar91xx_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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ar71xx_ref_freq = 5 * 1000 * 1000;
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pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
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freq = div * ar71xx_ref_freq;
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ar71xx_cpu_freq = freq;
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div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init ar71xx_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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ar71xx_ref_freq = 40 * 1000 * 1000;
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pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
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freq = div * ar71xx_ref_freq;
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div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
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ar71xx_cpu_freq = freq / div;
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div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init ar724x_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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ar71xx_ref_freq = 5 * 1000 * 1000;
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pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
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freq = div * ar71xx_ref_freq;
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div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
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freq *= div;
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ar71xx_cpu_freq = freq;
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div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init ar933x_detect_sys_frequency(void)
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{
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u32 clock_ctrl;
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u32 cpu_config;
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u32 freq;
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u32 t;
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t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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ar71xx_ref_freq = (40 * 1000 * 1000);
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else
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ar71xx_ref_freq = (25 * 1000 * 1000);
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clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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ar71xx_cpu_freq = ar71xx_ref_freq;
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ar71xx_ahb_freq = ar71xx_ref_freq;
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ar71xx_ddr_freq = ar71xx_ref_freq;
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} else {
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cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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freq = ar71xx_ref_freq / t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR933X_PLL_CPU_CONFIG_NINT_MASK;
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freq *= t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (t == 0)
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t = 1;
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freq >>= t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
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ar71xx_cpu_freq = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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ar71xx_ahb_freq = freq / t;
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}
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}
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static void __init detect_sys_frequency(void)
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{
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ar71xx_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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ar724x_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ar91xx_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR9330:
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case AR71XX_SOC_AR9331:
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ar933x_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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ar934x_detect_sys_frequency();
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break;
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default:
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BUG();
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}
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}
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const char *get_system_type(void)
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{
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return ar71xx_sys_type;
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}
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unsigned int __cpuinit get_c0_compare_irq(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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void __init plat_mem_setup(void)
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{
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set_io_port_base(KSEG1);
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ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
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AR71XX_DDR_CTRL_SIZE);
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ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
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AR71XX_PLL_SIZE);
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ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
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AR71XX_RESET_SIZE);
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ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
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ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
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AR71XX_USB_CTRL_SIZE);
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ar71xx_detect_mem_size();
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ar71xx_detect_sys_type();
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detect_sys_frequency();
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pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
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"Ref:%u.%03uMHz",
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ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
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ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000,
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ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
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ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000);
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_machine_restart = ar71xx_restart;
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_machine_halt = ar71xx_halt;
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pm_power_off = ar71xx_halt;
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}
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void __init plat_time_init(void)
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{
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mips_hpt_frequency = ar71xx_cpu_freq / 2;
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}
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__setup("board=", mips_machtype_setup);
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static int __init ar71xx_machine_setup(void)
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{
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ar71xx_gpio_init();
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ar71xx_add_device_uart();
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ar71xx_add_device_wdt();
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mips_machine_setup();
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return 0;
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}
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arch_initcall(ar71xx_machine_setup);
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static void __init ar71xx_generic_init(void)
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{
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/* Nothing to do */
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}
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MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
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ar71xx_generic_init);
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