98 lines
2.8 KiB
Diff
98 lines
2.8 KiB
Diff
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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@@ -40,6 +40,15 @@
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#define MIPS_CPU_TIMER_IRQ 7
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+#ifdef CONFIG_SOC_AMAZON_SE
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+#define LTQ_DMA_CH0_INT (INT_NUM_IM3_IRL0)
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+#define LTQ_DMA_CH1_INT (INT_NUM_IM3_IRL0 + 1)
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+#define LTQ_DMA_CH2_INT (INT_NUM_IM3_IRL0 + 2)
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+#define LTQ_DMA_CH3_INT (INT_NUM_IM3_IRL0 + 3)
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+#define LTQ_DMA_CH4_INT (INT_NUM_IM3_IRL0 + 4)
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+#define LTQ_DMA_CH5_INT (INT_NUM_IM3_IRL0 + 5)
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+#define LTQ_DMA_CH6_INT (INT_NUM_IM3_IRL0 + 6)
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+#else
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#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
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#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
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@@ -47,6 +56,7 @@
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#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
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#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
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#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
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+#endif
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#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
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#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
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#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -128,6 +128,11 @@
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extern void ltq_pmu_enable(unsigned int module);
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extern void ltq_pmu_disable(unsigned int module);
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+static inline int ltq_is_ase(void)
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+{
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+ return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
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+}
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+
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static inline int ltq_is_ar9(void)
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{
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return (ltq_get_soc_type() == SOC_TYPE_AR9);
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--- a/arch/mips/lantiq/xway/mach-easy50601.c
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+++ b/arch/mips/lantiq/xway/mach-easy50601.c
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@@ -41,9 +41,14 @@
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.parts = easy50601_partitions,
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};
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+static struct ltq_eth_data ltq_eth_data = {
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+ .mii_mode = -1, /* use EPHY */
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+};
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+
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static void __init easy50601_init(void)
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{
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ltq_register_nor(&easy50601_flash_data);
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+ ltq_register_etop(<q_eth_data);
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}
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MIPS_MACHINE(LTQ_MACH_EASY50601,
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--- a/drivers/net/lantiq_etop.c
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+++ b/drivers/net/lantiq_etop.c
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@@ -72,7 +72,11 @@
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/* use 2 static channels for TX/RX */
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#define LTQ_ETOP_TX_CHANNEL 1
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+#ifdef CONFIG_SOC_AMAZON_SE
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+#define LTQ_ETOP_RX_CHANNEL 5
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+#else
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#define LTQ_ETOP_RX_CHANNEL 6
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+#endif
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#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
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#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
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@@ -255,6 +259,9 @@
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}
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static int
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+ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data);
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+
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+static int
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ltq_etop_hw_init(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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@@ -274,6 +281,16 @@
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break;
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default:
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+ if (ltq_is_ase()) {
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+#define PMU_EPHY 0x80
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+#define LTQ_CGU_IFCCR 0x0018
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+ ltq_pmu_enable(PMU_EPHY);
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+ ltq_etop_w32_mask(0, 1, LTQ_ETOP_CFG);
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+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (0x1 << 4), LTQ_CGU_IFCCR);
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+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
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+ printk("Selected EPHY mode \n");
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+ break;
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+ }
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netdev_err(dev, "unknown mii mode %d\n",
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priv->pldata->mii_mode);
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return -ENOTSUPP;
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