eb75d320d1
A previous backported patch that adds freq/voltage operating points for the IMX6DL processor can cause hang/crash (general instability) on IMX6DL processors in the industrial/automative speed grades as they don't support 1GHz operation. This adds another backported patch from mainline that uses IMX6 fuse settings to properly remove invalid operating points for the particular CPU grade used. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 42294
76 lines
2.3 KiB
Diff
76 lines
2.3 KiB
Diff
From c962a0996335fae7f79e64677f47d4784b86f692 Mon Sep 17 00:00:00 2001
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From: Anson Huang <b20788@freescale.com>
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Date: Wed, 12 Feb 2014 17:57:03 +0800
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Subject: [PATCH] ARM: imx: add speed grading check for i.mx6 soc
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The fuse map of speed_grading[1:0] defines the max speed
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of ARM, see below the definition:
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2b'11: 1200000000Hz;
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2b'10: 996000000Hz;
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2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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2b'00: 792000000Hz;
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Need to remove all illegal setpoints according to fuse
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map.
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Signed-off-by: Anson Huang <b20788@freescale.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/mach-imx/mach-imx6q.c | 26 +++++++++++++++++++++++---
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1 file changed, 23 insertions(+), 3 deletions(-)
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--- a/arch/arm/mach-imx/mach-imx6q.c
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+++ b/arch/arm/mach-imx/mach-imx6q.c
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@@ -219,8 +219,10 @@ static void __init imx6q_init_machine(vo
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#define OCOTP_CFG3 0x440
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#define OCOTP_CFG3_SPEED_SHIFT 16
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#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
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+#define OCOTP_CFG3_SPEED_996MHZ 0x2
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+#define OCOTP_CFG3_SPEED_852MHZ 0x1
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-static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
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+static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
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{
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struct device_node *np;
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void __iomem *base;
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@@ -238,11 +240,29 @@ static void __init imx6q_opp_check_1p2gh
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goto put_node;
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}
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+ /*
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+ * SPEED_GRADING[1:0] defines the max speed of ARM:
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+ * 2b'11: 1200000000Hz;
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+ * 2b'10: 996000000Hz;
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+ * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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+ * 2b'00: 792000000Hz;
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+ * We need to set the max speed of ARM according to fuse map.
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+ */
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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- if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
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+ val &= 0x3;
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+
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+ if (val != OCOTP_CFG3_SPEED_1P2GHZ)
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if (dev_pm_opp_disable(cpu_dev, 1200000000))
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pr_warn("failed to disable 1.2 GHz OPP\n");
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+ if (val < OCOTP_CFG3_SPEED_996MHZ)
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+ if (dev_pm_opp_disable(cpu_dev, 996000000))
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+ pr_warn("failed to disable 996 MHz OPP\n");
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+ if (cpu_is_imx6q()) {
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+ if (val != OCOTP_CFG3_SPEED_852MHZ)
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+ if (dev_pm_opp_disable(cpu_dev, 852000000))
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+ pr_warn("failed to disable 852 MHz OPP\n");
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+ }
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put_node:
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of_node_put(np);
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@@ -268,7 +288,7 @@ static void __init imx6q_opp_init(void)
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goto put_node;
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}
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- imx6q_opp_check_1p2ghz(cpu_dev);
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+ imx6q_opp_check_speed_grading(cpu_dev);
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put_node:
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of_node_put(np);
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