133 lines
2.9 KiB
C
133 lines
2.9 KiB
C
/*
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* Ralink RT305X clock API
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/rt305x.h>
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#include <asm/mach-ralink/rt305x_regs.h>
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#include "common.h"
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struct clk {
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unsigned long rate;
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};
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static struct clk rt305x_cpu_clk;
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static struct clk rt305x_sys_clk;
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static struct clk rt305x_wdt_clk;
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static struct clk rt305x_uart_clk;
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void __init rt305x_clocks_init(void)
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{
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u32 t;
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t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
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if (soc_is_rt305x() || soc_is_rt3350()) {
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t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
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RT305X_SYSCFG_CPUCLK_MASK;
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switch (t) {
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case RT305X_SYSCFG_CPUCLK_LOW:
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rt305x_cpu_clk.rate = 320000000;
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break;
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case RT305X_SYSCFG_CPUCLK_HIGH:
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rt305x_cpu_clk.rate = 384000000;
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break;
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}
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rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
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rt305x_uart_clk.rate = rt305x_sys_clk.rate;
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rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
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} else if (soc_is_rt3352()) {
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t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
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RT3352_SYSCFG0_CPUCLK_MASK;
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switch (t) {
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case RT3352_SYSCFG0_CPUCLK_LOW:
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rt305x_cpu_clk.rate = 384000000;
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break;
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case RT3352_SYSCFG0_CPUCLK_HIGH:
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rt305x_cpu_clk.rate = 400000000;
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break;
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}
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rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
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rt305x_uart_clk.rate = 40000000;
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rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
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} else if (soc_is_rt5350()) {
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t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
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RT5350_SYSCFG0_CPUCLK_MASK;
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switch (t) {
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case RT5350_SYSCFG0_CPUCLK_360:
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rt305x_cpu_clk.rate = 360000000;
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rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
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break;
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case RT5350_SYSCFG0_CPUCLK_320:
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rt305x_cpu_clk.rate = 320000000;
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rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4;
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break;
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case RT5350_SYSCFG0_CPUCLK_300:
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rt305x_cpu_clk.rate = 300000000;
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rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
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break;
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default:
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BUG();
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}
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rt305x_uart_clk.rate = 40000000;
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rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
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} else {
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BUG();
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}
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}
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/*
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* Linux clock API
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*/
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struct clk *clk_get(struct device *dev, const char *id)
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{
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if (!strcmp(id, "sys"))
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return &rt305x_sys_clk;
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if (!strcmp(id, "cpu"))
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return &rt305x_cpu_clk;
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if (!strcmp(id, "wdt"))
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return &rt305x_wdt_clk;
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if (!strcmp(id, "uart"))
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return &rt305x_uart_clk;
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return ERR_PTR(-ENOENT);
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}
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EXPORT_SYMBOL(clk_get);
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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