af015f956c
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH SVN-Revision: 29868
32 lines
1.1 KiB
Diff
32 lines
1.1 KiB
Diff
From 781c5ae32a2e8aede2e1756dfbea1abb3cf09ffc Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 5 Jun 2011 23:38:44 +0200
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Subject: [PATCH 01/27] MIPS: ath79: Change number of available IRQs
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The status register of the miscellaneous interrupt controller is 32 bits
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wide, but the actual value of NR_IRQS covers only 8 of them. Change
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NR_IRQS in order to make all of those interrupt lines usable.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/2441/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/include/asm/mach-ath79/irq.h | 4 ++--
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1 files changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/mips/include/asm/mach-ath79/irq.h
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+++ b/arch/mips/include/asm/mach-ath79/irq.h
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@@ -10,10 +10,10 @@
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#define __ASM_MACH_ATH79_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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-#define NR_IRQS 16
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+#define NR_IRQS 40
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#define ATH79_MISC_IRQ_BASE 8
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-#define ATH79_MISC_IRQ_COUNT 8
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+#define ATH79_MISC_IRQ_COUNT 32
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#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
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#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
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