02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
124 lines
2.8 KiB
Diff
124 lines
2.8 KiB
Diff
From b9eaa80146abb09bcc7e6d8b33fca476453c839c Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Wed, 14 May 2014 22:01:16 -0500
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Subject: [PATCH 137/182] ARM: qcom-ipq8064-ap148: Add SPI related bindings
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 42 ++++++++++++++++++++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 47 ++++++++++++++++++++++++++++++
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2 files changed, 89 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -20,6 +20,15 @@
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function = "gsbi4";
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bias-disable;
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};
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+
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+ spi_pins: spi_pins {
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+ mux {
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+ pins = "gpio18", "gpio19", "gpio21";
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+ function = "gsbi5";
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+ drive-strength = <10>;
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+ bias-none;
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+ };
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+ };
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};
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gsbi@16300000 {
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@@ -38,5 +47,38 @@
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pinctrl-names = "default";
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};
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};
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+
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+ gsbi5: gsbi@1a200000 {
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+ qcom,mode = <GSBI_PROT_SPI>;
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+ status = "ok";
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+
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+ spi4: spi@1a280000 {
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+ status = "ok";
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+ spi-max-frequency = <50000000>;
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+
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+ pinctrl-0 = <&spi_pins>;
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+ pinctrl-names = "default";
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+
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+ cs-gpios = <&qcom_pinmux 20 0>;
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+
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+ flash: m25p80@0 {
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+ compatible = "s25fl256s1";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <50000000>;
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+ reg = <0>;
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+
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+ partition@0 {
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+ label = "rootfs";
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+ reg = <0x0 0x1000000>;
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+ };
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+
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+ partition@1 {
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+ label = "scratch";
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+ reg = <0x1000000 0x1000000>;
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+ };
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+ };
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+ };
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -187,6 +187,53 @@
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};
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};
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+ gsbi5: gsbi@1a200000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x1a200000 0x100>;
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+ clocks = <&gcc GSBI5_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ serial@1a240000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x1a240000 0x1000>,
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+ <0x1a200000 0x1000>;
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+ interrupts = <0 154 0x0>;
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+ clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ i2c@1a280000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x1a280000 0x1000>;
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+ interrupts = <0 155 0>;
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+
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+ clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi@1a280000 {
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+ compatible = "qcom,spi-qup-v1.1.1";
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+ reg = <0x1a280000 0x1000>;
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+ interrupts = <0 155 0>;
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+
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+ clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x00500000 0x1000>;
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