9aa196e0f2
Refresh patches, following required reworking: ar71xx/patches-4.9/930-chipidea-pullup.patch layerscape/patches-4.9/302-dts-support-layercape.patch sunxi/patches-4.9/0052-stmmac-form-4-12.patch Fixes for CVEs: CVE-2018-1108 CVE-2018-1092 Tested on: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Arjen de Korte <build+openwrt@de-korte.org>
26 lines
912 B
Diff
26 lines
912 B
Diff
--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -761,6 +761,13 @@ config SPI_TLE62X0
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sysfs interface, with each line presented as a kind of GPIO
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exposing both switch control and diagnostic feedback.
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+config SPI_RB4XX_CPLD
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+ tristate "MikroTik RB4XX CPLD driver"
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+ depends on ATH79_MACH_RB4XX
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+ help
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+ SPI driver for the Xilinx CPLD chip present on the
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+ MikroTik RB4xx boards.
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+
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#
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# Add new SPI protocol masters in alphabetical order above this line
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#
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -73,6 +73,7 @@ spi-pxa2xx-platform-objs := spi-pxa2xx.
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obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
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obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
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+obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o
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obj-$(CONFIG_SPI_QUP) += spi-qup.o
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obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
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obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
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