163 lines
4.3 KiB
Diff
163 lines
4.3 KiB
Diff
--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -52,6 +52,7 @@
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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+#ifdef CONFIG_SOC_XWAY
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static unsigned short ltq_eiu_irq[MAX_EIU] = {
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LTQ_EIU_IR0,
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LTQ_EIU_IR1,
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@@ -60,6 +61,7 @@ static unsigned short ltq_eiu_irq[MAX_EI
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LTQ_EIU_IR4,
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LTQ_EIU_IR5,
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};
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+#endif
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static struct resource ltq_icu_resource = {
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.name = "icu",
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@@ -68,15 +70,19 @@ static struct resource ltq_icu_resource
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.flags = IORESOURCE_MEM,
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};
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+#ifdef CONFIG_SOC_XWAY
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static struct resource ltq_eiu_resource = {
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.name = "eiu",
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.start = LTQ_EIU_BASE_ADDR,
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.end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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+#endif
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static void __iomem *ltq_icu_membase;
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+#ifdef CONFIG_SOC_XWAY
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static void __iomem *ltq_eiu_membase;
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+#endif
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void ltq_disable_irq(struct irq_data *d)
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{
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@@ -122,6 +128,7 @@ void ltq_enable_irq(struct irq_data *d)
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ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
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}
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+#ifdef CONFIG_SOC_XWAY
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static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
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{
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int i;
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@@ -161,6 +168,7 @@ static void ltq_shutdown_eiu_irq(struct
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}
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}
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}
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+#endif
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static struct irq_chip ltq_irq_type = {
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"icu",
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@@ -172,6 +180,7 @@ static struct irq_chip ltq_irq_type = {
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.irq_mask_ack = ltq_mask_and_ack_irq,
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};
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+#ifdef CONFIG_SOC_XWAY
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static struct irq_chip ltq_eiu_type = {
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"eiu",
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.irq_startup = ltq_startup_eiu_irq,
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@@ -183,6 +192,7 @@ static struct irq_chip ltq_eiu_type = {
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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};
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+#endif
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static void ltq_hw_irqdispatch(int module)
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{
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@@ -198,10 +208,12 @@ static void ltq_hw_irqdispatch(int modul
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irq = __fls(irq);
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do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
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+#ifdef CONFIG_SOC_XWAY
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/* if this is a EBU irq, we need to ack it or get a deadlock */
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if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
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LTQ_EBU_PCC_ISTAT);
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+#endif
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}
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#define DEFINE_HWx_IRQDISPATCH(x) \
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@@ -264,6 +276,7 @@ void __init arch_init_irq(void)
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if (!ltq_icu_membase)
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panic("Failed to remap icu memory\n");
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+#ifdef CONFIG_SOC_XWAY
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if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
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panic("Failed to insert eiu memory\n");
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@@ -275,6 +288,7 @@ void __init arch_init_irq(void)
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resource_size(<q_eiu_resource));
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if (!ltq_eiu_membase)
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panic("Failed to remap eiu memory\n");
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+#endif
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/* make sure all irqs are turned off by default */
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for (i = 0; i < 5; i++)
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@@ -300,6 +314,7 @@ void __init arch_init_irq(void)
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for (i = INT_NUM_IRQ0;
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i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
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+#ifdef CONFIG_SOC_XWAY
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if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
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(i == LTQ_EIU_IR2))
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irq_set_chip_and_handler(i, <q_eiu_type,
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@@ -310,6 +325,7 @@ void __init arch_init_irq(void)
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irq_set_chip_and_handler(i, <q_eiu_type,
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handle_level_irq);
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else
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+#endif
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irq_set_chip_and_handler(i, <q_irq_type,
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handle_level_irq);
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--- a/arch/mips/lantiq/clk.c
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+++ b/arch/mips/lantiq/clk.c
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@@ -46,6 +46,7 @@ static struct clk cpu_clk_generic[] = {
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},
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};
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+#ifdef CONFIG_SOC_XWAY
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static struct resource ltq_cgu_resource = {
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.name = "cgu",
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.start = LTQ_CGU_BASE_ADDR,
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@@ -55,6 +56,7 @@ static struct resource ltq_cgu_resource
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/* remapped clock register range */
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void __iomem *ltq_cgu_membase;
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+#endif
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void clk_init(void)
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{
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@@ -131,6 +133,7 @@ void __init plat_time_init(void)
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{
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struct clk *clk;
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+#ifdef CONFIG_SOC_XWAY
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if (insert_resource(&iomem_resource, <q_cgu_resource) < 0)
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panic("Failed to insert cgu memory\n");
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@@ -144,6 +147,7 @@ void __init plat_time_init(void)
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pr_err("Failed to remap cgu memory\n");
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unreachable();
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}
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+#endif
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clk = clk_get(0, "cpu");
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mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
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write_c0_compare(read_c0_count());
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--- a/arch/mips/lantiq/early_printk.c
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+++ b/arch/mips/lantiq/early_printk.c
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@@ -13,7 +13,11 @@
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#include <lantiq_soc.h>
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/* no ioremap possible at this early stage, lets use KSEG1 instead */
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+#ifdef CONFIG_SOC_FALCON
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+#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
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+#else
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#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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+#endif
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#define ASC_BUF 1024
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#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048))
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#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020))
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