cf50f72069
PLL for eth0 internal clock on ar913x is at 0x18050014 and AR913X_ETH0_PLL_SHIFT is 20 instead of 17 Signed-off-by: Chuanhong Guo <gch981213@gmail.com> |
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imagebuilder | ||
linux | ||
sdk | ||
toolchain | ||
Config.in | ||
Makefile |