cd54b2d42b
- Refreshed all patches - Removed upstreamed - Adapted 4 patches: 473-fix-marvell-phy-initialization-issues.patch ----------------------------------------------- Removed hunk 5 which got upstreamed 403-net-phy-avoid-setting-unsupported-EEE-advertisments.patch 404-net-phy-restart-phy-autonegotiation-after-EEE-advert.patch -------------------------------------------------------------- Adapted these 2 RFC patches, merging the delta's from an upstream commit (see below) which made it before these 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux- stable.git/commit/?h=v4.9.36&id=97ace183074d306942b903a148aebd5d061758f0 180-usb-xhci-add-support-for-performing-fake-doorbell.patch ----------------------------------------------------------- - Moved fake_doorbell bitmask due to new item Compile tested on: cns3xxx, imx6 Run tested on: cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
150 lines
4.8 KiB
Diff
150 lines
4.8 KiB
Diff
From 3274ba26f27becfc4193ec6e229288140651f240 Mon Sep 17 00:00:00 2001
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From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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Date: Thu, 27 Oct 2016 12:03:57 +0200
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Subject: [PATCH] mtd: spi-nor: add a stateless method to support memory size
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above 128Mib
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This patch provides an alternative mean to support memory above 16MiB
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(128Mib) by replacing 3byte address op codes by their associated 4byte
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address versions.
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Using the dedicated 4byte address op codes doesn't change the internal
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state of the SPI NOR memory as opposed to using other means such as
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updating a Base Address Register (BAR) and sending command to enter/leave
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the 4byte mode.
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Hence when a CPU reset occurs, early bootloaders don't need to be aware
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of BAR value or 4byte mode being enabled: they can still access the first
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16MiB of the SPI NOR memory using the regular 3byte address op codes.
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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Tested-by: Vignesh R <vigneshr@ti.com>
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Acked-by: Marek Vasut <marek.vasut@gmail.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 101 +++++++++++++++++++++++++++++++++---------
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1 file changed, 80 insertions(+), 21 deletions(-)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -81,6 +81,10 @@ struct flash_info {
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* because it has the same value as
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* ATMEL flashes)
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*/
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+#define SPI_NOR_4B_OPCODES BIT(11) /*
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+ * Use dedicated 4byte address op codes
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+ * to support memory size above 128Mib.
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+ */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@@ -194,6 +198,78 @@ static inline struct spi_nor *mtd_to_spi
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return mtd->priv;
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}
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+
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+static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
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+{
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+ size_t i;
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+
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+ for (i = 0; i < size; i++)
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+ if (table[i][0] == opcode)
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+ return table[i][1];
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+
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+ /* No conversion found, keep input op code. */
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+ return opcode;
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+}
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+
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+static inline u8 spi_nor_convert_3to4_read(u8 opcode)
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+{
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+ static const u8 spi_nor_3to4_read[][2] = {
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+ { SPINOR_OP_READ, SPINOR_OP_READ_4B },
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+ { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
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+ { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
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+ { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
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+ { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
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+ { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
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+ };
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+
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+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
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+ ARRAY_SIZE(spi_nor_3to4_read));
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+}
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+
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+static inline u8 spi_nor_convert_3to4_program(u8 opcode)
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+{
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+ static const u8 spi_nor_3to4_program[][2] = {
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+ { SPINOR_OP_PP, SPINOR_OP_PP_4B },
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+ { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
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+ { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
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+ };
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+
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+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
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+ ARRAY_SIZE(spi_nor_3to4_program));
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+}
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+
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+static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
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+{
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+ static const u8 spi_nor_3to4_erase[][2] = {
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+ { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
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+ { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
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+ { SPINOR_OP_SE, SPINOR_OP_SE_4B },
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+ };
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+
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+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
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+ ARRAY_SIZE(spi_nor_3to4_erase));
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+}
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+
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+static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
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+ const struct flash_info *info)
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+{
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+ /* Do some manufacturer fixups first */
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+ switch (JEDEC_MFR(info)) {
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+ case SNOR_MFR_SPANSION:
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+ /* No small sector erase for 4-byte command set */
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+ nor->erase_opcode = SPINOR_OP_SE;
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+ nor->mtd.erasesize = info->sector_size;
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+ break;
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+
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+ default:
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+ break;
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+ }
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+
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+ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
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+ nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
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+ nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
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+}
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+
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/* Enable/disable 4-byte addressing mode. */
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static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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int enable)
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@@ -1628,27 +1704,10 @@ int spi_nor_scan(struct spi_nor *nor, co
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else if (mtd->size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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- if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
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- /* Dedicated 4-byte command set */
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- switch (nor->flash_read) {
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- case SPI_NOR_QUAD:
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- nor->read_opcode = SPINOR_OP_READ_1_1_4_4B;
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- break;
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- case SPI_NOR_DUAL:
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- nor->read_opcode = SPINOR_OP_READ_1_1_2_4B;
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- break;
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- case SPI_NOR_FAST:
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- nor->read_opcode = SPINOR_OP_READ_FAST_4B;
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- break;
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- case SPI_NOR_NORMAL:
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- nor->read_opcode = SPINOR_OP_READ_4B;
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- break;
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- }
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- nor->program_opcode = SPINOR_OP_PP_4B;
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- /* No small sector erase for 4-byte command set */
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- nor->erase_opcode = SPINOR_OP_SE_4B;
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- mtd->erasesize = info->sector_size;
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- } else
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+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
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+ info->flags & SPI_NOR_4B_OPCODES)
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+ spi_nor_set_4byte_opcodes(nor, info);
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+ else
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set_4byte(nor, info, 1);
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} else {
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nor->addr_width = 3;
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