c7bf2accc9
These are cherry-picked & backported from LKML: *https://lkml.org/lkml/2015/3/17/19 They are enabled on both 3.18 and 4.1 kernel. Patches 150 to 154 are applying changes merged since 3.18; they enable mechanisms used by the ADM driver. ADM engine is used by the NAND controller, so it is necessary to bring-up NAND flash support. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46567
210 lines
4.5 KiB
Diff
210 lines
4.5 KiB
Diff
From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001
|
|
From: Mathieu Olivari <mathieu@codeaurora.org>
|
|
Date: Mon, 11 May 2015 12:29:18 -0700
|
|
Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms
|
|
|
|
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++
|
|
arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++
|
|
arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++
|
|
3 files changed, 160 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
|
@@ -71,6 +71,16 @@
|
|
bias-disable;
|
|
};
|
|
};
|
|
+
|
|
+ rgmii2_pins: rgmii2_pins {
|
|
+ mux {
|
|
+ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
|
+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
|
+ function = "rgmii2";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
};
|
|
|
|
gsbi@16300000 {
|
|
@@ -188,5 +198,26 @@
|
|
reg = <4>;
|
|
};
|
|
};
|
|
+
|
|
+ gmac1: ethernet@37200000 {
|
|
+ status = "ok";
|
|
+ phy-mode = "rgmii";
|
|
+ phy-handle = <&phy4>;
|
|
+ qcom,id = <1>;
|
|
+
|
|
+ pinctrl-0 = <&rgmii2_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ };
|
|
+
|
|
+ gmac2: ethernet@37400000 {
|
|
+ status = "ok";
|
|
+ phy-mode = "sgmii";
|
|
+ qcom,id = <2>;
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
|
@@ -75,6 +75,14 @@
|
|
bias-disable;
|
|
};
|
|
};
|
|
+
|
|
+ rgmii0_pins: rgmii0_pins {
|
|
+ mux {
|
|
+ pins = "gpio2", "gpio66";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
};
|
|
|
|
gsbi2: gsbi@12480000 {
|
|
@@ -225,5 +233,40 @@
|
|
reg = <7>;
|
|
};
|
|
};
|
|
+
|
|
+ gmac0: ethernet@37000000 {
|
|
+ status = "ok";
|
|
+ phy-mode = "rgmii";
|
|
+ qcom,id = <0>;
|
|
+ phy-handle = <&phy4>;
|
|
+
|
|
+ pinctrl-0 = <&rgmii0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ };
|
|
+
|
|
+ gmac1: ethernet@37200000 {
|
|
+ status = "ok";
|
|
+ phy-mode = "sgmii";
|
|
+ qcom,id = <1>;
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gmac2: ethernet@37400000 {
|
|
+ status = "ok";
|
|
+ phy-mode = "sgmii";
|
|
+ qcom,id = <2>;
|
|
+ phy-handle = <&phy6>;
|
|
+ };
|
|
+
|
|
+ gmac3: ethernet@37600000 {
|
|
+ status = "ok";
|
|
+ phy-mode = "sgmii";
|
|
+ qcom,id = <3>;
|
|
+ phy-handle = <&phy7>;
|
|
+ };
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
@@ -615,5 +615,91 @@
|
|
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ nss_common: syscon@03000000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x03000000 0x0000FFFF>;
|
|
+ };
|
|
+
|
|
+ qsgmii_csr: syscon@1bb00000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x1bb00000 0x000001FF>;
|
|
+ };
|
|
+
|
|
+ gmac0: ethernet@37000000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac";
|
|
+ reg = <0x37000000 0x200000>;
|
|
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE1_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac1: ethernet@37200000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac";
|
|
+ reg = <0x37200000 0x200000>;
|
|
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE2_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE2_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac2: ethernet@37400000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac";
|
|
+ reg = <0x37400000 0x200000>;
|
|
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE3_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE3_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac3: ethernet@37600000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac";
|
|
+ reg = <0x37600000 0x200000>;
|
|
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE4_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE4_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
};
|